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    Apparatus for data retention and supply noise mitigation using clamps
    1.
    发明授权
    Apparatus for data retention and supply noise mitigation using clamps 有权

    公开(公告)号：US10418076B2

    公开(公告)日：2019-09-17

    申请号：US15706521

    申请日：2017-09-15

    Applicant: Intel Corporation

    Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

    IPC: G11C5/14

    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

    Apparatus for data retention and supply noise mitigation using clamps
    4.
    发明授权
    Apparatus for data retention and supply noise mitigation using clamps 有权

    公开(公告)号：US09766827B1

    公开(公告)日：2017-09-19

    申请号：US15151402

    申请日：2016-05-10

    Applicant: Intel Corporation

    Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

    IPC: G05F1/613 ,  G06F3/06 ,  G11C5/14

    CPC classification number: G11C5/148

    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

    Multi-bit pulsed latch including serial scan chain
    5.
    发明授权
    Multi-bit pulsed latch including serial scan chain 有权

    公开(公告)号：US10410699B1

    公开(公告)日：2019-09-10

    申请号：US16024441

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Anupama A. Thaploo ,  Bhushan Borole ,  Muhammad M. Khellah ,  Pascal A. Meinerzhagen

    IPC: G11C7/22 ,  G01R31/3185

    Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

    APPARATUS AND METHOD FOR DETECTING OR REPAIRING MINIMUM DELAY ERRORS
    6.
    发明申请
    APPARATUS AND METHOD FOR DETECTING OR REPAIRING MINIMUM DELAY ERRORS 有权
    检测或修复最小延迟错误的装置和方法

    公开(公告)号：US20160173090A1

    公开(公告)日：2016-06-16

    申请号：US14572031

    申请日：2014-12-16

    Applicant: Intel Corporation

    Inventor： Pascal A. Meinerzhagen ,  Sandip Kundu ,  James W. Tschanz ,  Vivek K. De

    IPC: H03K19/003 ,  H03K3/037

    CPC classification number: H03K19/00323 ,  H03K5/26

    Abstract: Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

    Abstract translation: 描述了用于检测或修复最小延迟误差的装置和方法。 该装置可以包括用于接收时钟信号和数据路径信号的最小延迟误差检测器（MDED），并且基于所接收的数据路径信号和时钟信号来检测数据路径中的最小延迟误差（MDE）。 可以通过调整耦合到MDED的一个或多个区域时钟缓冲器来修复MDE。 此外，该装置可以包括用于在正常系统操作期间检测和修复MDE的最小延迟路径副本（MDPR）。 可以描述和/或要求保护其他实施例。

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