公开(公告)号：US11437283B2

公开(公告)日：2022-09-06

申请号：US16355195

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffery D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US11672133B2

公开(公告)日：2023-06-06

申请号：US16447603

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick R. Morrow ,  Hui Jae Yoo ,  Sean T. Ma ,  Scott B. Clendenning ,  Abhishek A. Sharma ,  Ehren Mannebach ,  Urusa Alaan

IPC: H10B63/00 ,  H01L21/311 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B63/845 ,  H01L21/31116 ,  H01L21/7682 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

公开(公告)号：US12080605B2

公开(公告)日：2024-09-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffrey D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/785

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.