公开(公告)号：US20180095883A1

公开(公告)日：2018-04-05

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F12/0866 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

公开(公告)号：US09459985B2

公开(公告)日：2016-10-04

申请号：US14229679

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Alexey Chinkov ,  Pavel Konev

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/36 ,  G06F13/00

CPC classification number: G06F11/348 ,  G06F11/3419 ,  G06F11/3636 ,  G06F11/3648 ,  G06F13/00

Abstract: Methods and apparatuses may provide for tracing the performance of BIOS from the start of its execution. A hardware device such as a hardware probe may be connected to the processor on a target board and used to gather and transfer data to a host computer without resort to a COM port.

Abstract translation: 方法和设备可以提供从执行开始跟踪BIOS的性能。 诸如硬件探测器的硬件设备可以连接到目标板上的处理器，并用于收集和传送数据到主机而不需要使用COM端口。

公开(公告)号：US10175992B2

公开(公告)日：2019-01-08

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F9/44 ,  G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

公开(公告)号：US09785604B2

公开(公告)日：2017-10-10

申请号：US13767881

申请日：2013-02-15

Applicant: Intel Corporation

Inventor： Ivan Herrera Mejia ,  Manuel A. Aguilar Arreola ,  Shrinivas Venkatraman ,  Andrea R. Vavra ,  Pavel Konev

IPC: G06F13/00 ,  G06F13/42 ,  G06F9/44 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F9/4411 ,  G06F13/385 ,  G06F13/4072 ,  G06F2213/0026

Abstract: Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.

公开(公告)号：US09026725B2

公开(公告)日：2015-05-05

申请号：US13728581

申请日：2012-12-27

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Zvika Greenfield ,  Christopher P. Mozak ,  Pavel Konev ,  Olga Fomenko

IPC: G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

Abstract translation: 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。