公开(公告)号：US20230086751A1

公开(公告)日：2023-03-23

申请号：US17483279

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Aliasgar Madraswala ,  Pranav Chava

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/30 ,  G11C16/08

Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

公开(公告)号：US12154627B2

公开(公告)日：2024-11-26

申请号：US17483279

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Aliasgar Madraswala ,  Pranav Chava

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/30

Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

公开(公告)号：US20230178158A1

公开(公告)日：2023-06-08

申请号：US17545672

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Soo-yong Park ,  Pranav Chava ,  Binh Ngo

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.

公开(公告)号：US11139036B2

公开(公告)日：2021-10-05

申请号：US16786948

申请日：2020-02-10

Applicant: INTEL CORPORATION

Inventor： Tarek Ahmed Ameen Beshari ,  Pranav Chava ,  Shantanu R. Rajwade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.