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公开(公告)号：US11056203B1
公开(公告)日：2021-07-06
申请号：US16788194
申请日：2020-02-11
Applicant: INTEL CORPORATION
Inventor： Xiang Yang , Pranav Kalavade , Ali Khakifirooz , Shantanu R. Rajwade , Sagar Upadhyay
Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.
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公开(公告)号：US12154627B2
公开(公告)日：2024-11-26
申请号：US17483279
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Aliasgar Madraswala , Pranav Chava
Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.
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3.发明授权公开(公告)号：US11139036B2
公开(公告)日：2021-10-05
申请号：US16786948
申请日：2020-02-10
Applicant: INTEL CORPORATION
Inventor： Tarek Ahmed Ameen Beshari , Pranav Chava , Shantanu R. Rajwade , Sagar Upadhyay
Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.
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公开(公告)号：US11923016B2
公开(公告)日：2024-03-05
申请号：US17033082
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Aliasgar S. Madraswala , Sagar Upadhyay , Jiantao Zhou
CPC classification number: G11C16/26 , G06F3/0611 , G11C16/10 , G11C16/3431 , G11C16/3495
Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.
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公开(公告)号：US20230086751A1
公开(公告)日：2023-03-23
申请号：US17483279
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Aliasgar Madraswala , Pranav Chava
Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.
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Patent Agency Ranking
公开(公告)号：US20230082368A1
公开(公告)日：2023-03-16
申请号：US17475880
申请日：2021-09-15
Applicant: Intel Corporation
Inventor： Chang Wan Ha , Binh Ngo , Ahsanur Rahman , Radhika Chinnammagari , Sagar Upadhyay
Abstract: Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.
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公开(公告)号：US20190043596A1
公开(公告)日：2019-02-07
申请号：US15838202
申请日：2017-12-11
Applicant: Intel Corporation
Inventor： Aliasgar S. Madraswala , Xin Guo , Ali Khakifirooz , Pranav Kalavade , Sagar Upadhyay
Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.
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公开(公告)号：US12211563B2
公开(公告)日：2025-01-28
申请号：US17411919
申请日：2021-08-25
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Archana Tankasala , Aliasgar S. Madraswala , Shantanu Rajwade
Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.
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公开(公告)号：US20230061293A1
公开(公告)日：2023-03-02
申请号：US17411919
申请日：2021-08-25
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Archana Tankasala , Aliasgar S. Madraswala , Shantanu Rajwade
Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.
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公开(公告)号：US20220101927A1
公开(公告)日：2022-03-31
申请号：US17033082
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Aliasgar S. Madraswala , Sagar Upadhyay , Jiantao Zhou
Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.
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