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    Cache processes with adaptive dynamic start voltage calculation for memory devices
    2.
    发明授权
    Cache processes with adaptive dynamic start voltage calculation for memory devices 有权

    公开(公告)号：US12224019B2

    公开(公告)日：2025-02-11

    申请号：US17213150

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

    IPC: G11C16/00 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

    Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

    Boosted bitlines for storage cell programmed state verification in a memory array
    4.
    发明授权
    Boosted bitlines for storage cell programmed state verification in a memory array 有权

    公开(公告)号：US11056203B1

    公开(公告)日：2021-07-06

    申请号：US16788194

    申请日：2020-02-11

    Applicant: INTEL CORPORATION

    Inventor： Xiang Yang ,  Pranav Kalavade ,  Ali Khakifirooz ,  Shantanu R. Rajwade ,  Sagar Upadhyay

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

    Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.

    Predictive count fail byte (CFBYTE) for non-volatile memory
    10.
    发明申请
    Predictive count fail byte (CFBYTE) for non-volatile memory 审中-公开

    公开(公告)号：US20170186497A1

    公开(公告)日：2017-06-29

    申请号：US14998119

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Pranav Kalavade

    IPC: G11C29/38 ,  G11C29/44 ,  G11C5/14

    CPC classification number: G11C29/38 ,  G11C5/148 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/44

    Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.

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