公开(公告)号：US10345885B2

公开(公告)日：2019-07-09

申请号：US15277936

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

IPC: G06F1/324 ,  G06F13/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

公开(公告)号：US20180088658A1

公开(公告)日：2018-03-29

申请号：US15277936

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

公开(公告)号：US20170212832A1

公开(公告)日：2017-07-27

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/42 ,  G06F13/12 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.