公开(公告)号：US20170212832A1

公开(公告)日：2017-07-27

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/42 ,  G06F13/12 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09910771B2

公开(公告)日：2018-03-06

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09535829B2

公开(公告)日：2017-01-03

申请号：US14128669

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract translation: 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

公开(公告)号：US10345885B2

公开(公告)日：2019-07-09

申请号：US15277936

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

IPC: G06F1/324 ,  G06F13/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

公开(公告)号：US20180088658A1

公开(公告)日：2018-03-29

申请号：US15277936

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

公开(公告)号：US09374004B2

公开(公告)日：2016-06-21

申请号：US13931604

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Ritesh B. Trivedi ,  James A. McCall ,  Aaron Martin

IPC: H03K19/0175 ,  H03K19/0185 ,  H02M3/158 ,  G11C29/02 ,  G11C7/10 ,  H04L25/02

CPC classification number: H02M3/158 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  H04L25/0276 ,  H04L25/029

Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

Abstract translation: 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。