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    Power control of a memory device through a sideband channel of a memory bus
    2.
    发明授权
    Power control of a memory device through a sideband channel of a memory bus 有权

    公开(公告)号：US10345885B2

    公开(公告)日：2019-07-09

    申请号：US15277936

    申请日：2016-09-27

    Applicant: INTEL CORPORATION

    Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

    IPC: G06F1/324 ,  G06F13/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

    Power Control of a Memory Device Through a Sideband Channel of a Memory Bus
    3.
    发明申请
    Power Control of a Memory Device Through a Sideband Channel of a Memory Bus 审中-公开

    公开(公告)号：US20180088658A1

    公开(公告)日：2018-03-29

    申请号：US15277936

    申请日：2016-09-27

    Applicant: INTEL CORPORATION

    Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

    In-system provisioning of firmware for a hardware platform
    6.
    发明授权
    In-system provisioning of firmware for a hardware platform 有权
    硬件平台固件的系统配置

    公开(公告)号：US09594910B2

    公开(公告)日：2017-03-14

    申请号：US14229708

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Nitin V. Sarangdhar ,  Robert J. Royer, Jr. ,  Eng Hun Ooi ,  Brian R. McFarlane ,  Mukesh Kataria

    IPC: G06F9/44 ,  G06F11/14 ,  G06F21/57

    CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4411 ,  G06F11/1417 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/03 ,  G06F2221/033

    Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

    Abstract translation: 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。

    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY
    7.
    发明申请
    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY 有权
    具有改进的信号完整性的下功率SCRAMBLING

    公开(公告)号：US20160188523A1

    公开(公告)日：2016-06-30

    申请号：US14583623

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Christopher P. Mozak ,  Brian R. McFarlane

    IPC: G06F13/42 ,  G06F13/28

    CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

    Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。

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