公开(公告)号：US10185696B2

公开(公告)日：2019-01-22

申请号：US15070481

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/00 ,  G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F1/32 ,  G06F9/4401

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

公开(公告)号：US09952619B2

公开(公告)日：2018-04-24

申请号：US14866237

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Brian R. McFarlane

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F13/40 ,  G06F13/4291 ,  H04J3/0697

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

公开(公告)号：US20170286357A1

公开(公告)日：2017-10-05

申请号：US15084555

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Anoop Mukker ,  Bharat Daga ,  David W. Vogel

IPC: G06F13/42 ,  H04L29/06

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H04L69/08

Abstract: In one embodiment, an apparatus comprises: a controller to communicate data having a format according to a first communication protocol, the controller comprising a Mobile Industry Processor Interface (MIPI)-compatible controller; an interface circuit coupled to the controller to receive the data, convert the data and communicate the converted data to a physical unit of a second communication protocol, the converted data having a format according to the second communication protocol; and the physical unit coupled to the interface circuit to receive and serialize the converted data and output the serialized converted data to a destination. Other embodiments are described and claimed.

公开(公告)号：US11625084B2

公开(公告)日：2023-04-11

申请号：US16542253

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Kuan Hau Tan ,  Anoop Mukker ,  Ang Li ,  Wai Ben Lin ,  Arash Talebi

IPC: G06F1/3215 ,  G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.

公开(公告)号：US20220197519A1

公开(公告)日：2022-06-23

申请号：US17128072

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Chia-Hung Kuo ,  Anoop Mukker ,  Eng Hun Ooi ,  Avishay Snir ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Wai Ben Lin

IPC: G06F3/06

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

公开(公告)号：US20220004668A1

公开(公告)日：2022-01-06

申请号：US17477202

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Prashant Dewan ,  Thomas Bowen ,  Anoop Mukker

IPC: G06F21/78 ,  G06F3/06 ,  H04L9/32

Abstract: Methods and apparatus relating to a lockable partition in NVMe (Non-Volatile Memory express) drives with drive migration support are described. In an embodiment, a Non-Volatile Memory (NVM) device stores data and partition logic circuitry locks or unlocks a partition on the NVM device in response to a command. The NVM device is physically migratable to a different platform and the NVM device is protected after power loss during runtime. The partition logic circuitry locks or unlocks the partition in response to the command and a cryptographic key. Other embodiments are also disclosed and claimed.

公开(公告)号：US10649484B2

公开(公告)日：2020-05-12

申请号：US15960074

申请日：2018-04-23

Applicant: INTEL CORPORATION

Inventor： Anoop Mukker ,  Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Brian R. McFarlane

IPC: G06F1/08 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42 ,  H04J3/06

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

公开(公告)号：US10168760B2

公开(公告)日：2019-01-01

申请号：US15074774

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Anoop Mukker ,  Daniel Nemiroff ,  Nobuyuki Suzuki ,  David W. Vogel

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26

Abstract: An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.

公开(公告)号：US12014081B2

公开(公告)日：2024-06-18

申请号：US17122158

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Anoop Mukker ,  Shankar Natarajan ,  Romesh Trivedi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

公开(公告)号：US20200226260A1

公开(公告)日：2020-07-16

申请号：US16832147

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Nivedita Aggarwal ,  Anoop Mukker ,  Michael Berger ,  Karunakara Kotary ,  Arijit Chattopadhyay ,  Rajesh Poornachandran

IPC: G06F21/57 ,  G06F21/56 ,  G06F11/14

Abstract: An apparatus to facilitate firmware resiliency in a computer system platform is disclosed. The apparatus comprises a first non-volatile memory to store primary firmware for a computer system platform, a second non-volatile memory to store a firmware copy of the primary firmware and a resiliency hardware, coupled to the first non-volatile memory via the system fabric, to detect unauthorized access to the primary firmware and restore the primary firmware stored in the first non-volatile memory with the firmware copy.