公开(公告)号：US20160182186A1

公开(公告)日：2016-06-23

申请号：US14578313

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

IPC: H04L1/00

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

公开(公告)号：US20190179786A1

公开(公告)日：2019-06-13

申请号：US16279485

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/54 ,  G06F13/40 ,  G06F9/455 ,  G06F13/10

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US10235302B2

公开(公告)日：2019-03-19

申请号：US15375582

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya

IPC: G06F12/128 ,  G06F12/0808

Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.

公开(公告)号：US10990546B2

公开(公告)日：2021-04-27

申请号：US16279485

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40 ,  G06F9/54

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US20200349100A1

公开(公告)日：2020-11-05

申请号：US16936078

申请日：2020-07-22

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/28 ,  G06F12/0866 ,  G06F3/06 ,  G06F11/10 ,  G06F13/10 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

公开(公告)号：US20180225237A1

公开(公告)日：2018-08-09

申请号：US15423949

申请日：2017-02-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F9/54 ,  G06F13/102 ,  G06F13/4068 ,  G06F2213/0026

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

公开(公告)号：US11449446B2

公开(公告)日：2022-09-20

申请号：US16936078

申请日：2020-07-22

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/0866 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F13/42 ,  G06F13/10

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

公开(公告)号：US09602237B2

公开(公告)日：2017-03-21

申请号：US14578313

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

IPC: G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H04L12/40

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

公开(公告)号：US20160335208A1

公开(公告)日：2016-11-17

申请号：US15224006

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G06F3/06 ,  G06F13/10

CPC classification number: G06F13/28 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F12/0866 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/262 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. For instance, there is disclosed a storage apparatus having therein a plurality of NAND (Negated AND) based flash memory components arranged into a plurality of NAND arrays; a NAND controller communicatively interfaced with the plurality of NAND arrays; and block mirroring logic to establish a mirrored copy for each data block written to the storage apparatus, each mirrored copy to be stored within one of plurality of NAND arrays. Other related embodiments are disclosed.

Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。 例如，公开了一种存储装置，其中具有排列成多个NAND阵列的多个基于NAND（Negated AND）的闪速存储器组件; 与多个NAND阵列通信地对接的NAND控制器; 和块镜像逻辑，以便为写入存储设备的每个数据块建立镜像拷贝，每个镜像拷贝存储在多个NAND阵列之一内。 公开了其他相关实施例。

公开(公告)号：US10241947B2

公开(公告)日：2019-03-26

申请号：US15423949

申请日：2017-02-03

Applicant: Intel Corporation

Inventor： Samantha J. Edirisooriya ,  Geetani R. Edirisooriya ,  Roger C. Jeppsen ,  Pankaj Kumar

IPC: G06F13/28 ,  G06F9/455 ,  G06F13/10 ,  G06F13/40 ,  G06F9/54

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.