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公开(公告)号：US20210384094A1
公开(公告)日：2021-12-09
申请号：US17406512
申请日：2021-08-19
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard Christopher Stamey , Amruthavalli Pallavi Alur
IPC: H01L23/13 , H01L23/498 , H01L23/538 , H01L23/488 , H01L23/485
Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
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公开(公告)号：US11923257B2
公开(公告)日：2024-03-05
申请号：US17406512
申请日：2021-08-19
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard Christopher Stamey , Amruthavalli Pallavi Alur
IPC: H01L23/498 , H01L23/13 , H01L23/485 , H01L23/488 , H01L23/538
CPC classification number: H01L23/13 , H01L23/485 , H01L23/488 , H01L23/49816 , H01L23/5383 , H01L23/5385 , H01L2224/16225 , H01L2924/15311
Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
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公开(公告)号：US20200335444A1
公开(公告)日：2020-10-22
申请号：US16918900
申请日：2020-07-01
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard C. Stamey
IPC: H01L23/538 , H01L21/683 , H01L21/48 , H01L23/498
Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
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公开(公告)号：US11114353B2
公开(公告)日：2021-09-07
申请号：US16080093
申请日：2016-03-30
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard Christopher Stamey , Amruthavalli Pallavi Alur
IPC: H01L23/13 , H01L23/498 , H01L23/538 , H01L23/488 , H01L23/485
Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
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公开(公告)号：US10716214B2
公开(公告)日：2020-07-14
申请号：US15771774
申请日：2015-12-03
Applicant: INTEL CORPORATION
Inventor： Robert Starkston , Richard C. Stamey , Robert L. Sankman , Scott M. Mokler
Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
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Patent Agency Ranking
公开(公告)号：US10763215B2
公开(公告)日：2020-09-01
申请号：US15774221
申请日：2015-12-09
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard C. Stamey
IPC: H01L23/538 , H01L21/683 , H01L21/48 , H01L23/498 , H01L25/065
Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
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公开(公告)号：US20190057937A1
公开(公告)日：2019-02-21
申请号：US15774221
申请日：2015-12-09
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard C. Stamey
IPC: H01L23/538 , H01L23/498
CPC classification number: H01L23/5385 , H01L21/486 , H01L21/6835 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49894 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0655 , H01L2221/68345
Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
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公开(公告)号：US20190057915A1
公开(公告)日：2019-02-21
申请号：US16080093
申请日：2016-03-30
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard Christopher Stamey , Amruthavalli Pallavi Alur
IPC: H01L23/13 , H01L23/538 , H01L23/498
Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
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公开(公告)号：US20250113561A1
公开(公告)日：2025-04-03
申请号：US18476624
申请日：2023-09-28
Applicant: Intel Corporation
Inventor： Rahul Ramaswamy , Marko Radosavljevic , Hsu-Yu Chang , Scott M. Mokler , Stephanie Chin , Walid M. Hafez
IPC: H01L29/06 , H01L27/092 , H01L29/423 , H01L29/778 , H01L29/78 , H01L29/786
Abstract: In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the isolation regions, a liner material is included between the strain material and the source and drain regions. Certain embodiments provide independent tuning of strain forces in a stacked transistor device. Different materials are selected for different layers in the stacked device to provide favorable performance enhancement or tuning (e.g., adjustment of the threshold voltage) in NMOS and PMOS layers.
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公开(公告)号：US11444033B2
公开(公告)日：2022-09-13
申请号：US16918900
申请日：2020-07-01
Applicant: Intel Corporation
Inventor： Robert Starkston , Robert L. Sankman , Scott M. Mokler , Richard C. Stamey
IPC: H01L23/538 , H01L21/683 , H01L21/48 , H01L23/498 , H01L25/065
Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.
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