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公开(公告)号：US09727267B1
公开(公告)日：2017-08-08
申请号：US15277524
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Donia Sebastian , Simon D. Ramage , Curtis A. Gittens , Scott Nelson , David B. Carlton , Kai-Uwe Schmidt
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0659 , G06F3/067 , G06F3/0688
Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.
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公开(公告)号：US10789124B2
公开(公告)日：2020-09-29
申请号：US16145983
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Lei Chen , Xin Guo , Shu-Jen Lee , Chu-hsiang Teng , Scott Nelson , Donia Sebastian
Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.
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公开(公告)号：US10095432B2
公开(公告)日：2018-10-09
申请号：US15656885
申请日：2017-07-21
Applicant: Intel Corporation
Inventor： Donia Sebastian , Simon D. Ramage , Curtis A. Gittens , Scott Nelson , David B. Carlton , Kai-Uwe Schmidt
Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.
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Patent Agency Ranking
公开(公告)号：US20180101323A1
公开(公告)日：2018-04-12
申请号：US15656885
申请日：2017-07-21
Applicant: Intel Corporation
Inventor： Donia Sebastian , Simon D. Ramage , Curtis A. Gittens , Scott Nelson , David B. Carlton , Kai-Uwe Schmidt
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0659 , G06F3/067 , G06F3/0688
Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.
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5.发明授权Using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units 有权使用来自多个存储单元和奇偶校验存储单元的可靠性信息来恢复存储单元中的一个存储单元的数据公开(公告)号：US09588841B2
公开(公告)日：2017-03-07
申请号：US14499078
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Andre Lei , Scott Nelson , Zion S. Kwok , Ravi H. Motwani
CPC classification number: G06F11/1068 , G06F11/1012 , G11C5/143 , G11C29/52 , H03M13/1105
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
Abstract translation: 提供了使用来自多个存储单元的可靠性信息和奇偶校验存储单元来恢复存储单元中的一个故障存储单元的数据的方法，系统和装置。 在包括目标数据存储单元和奇偶校验存储单元以外的数据存储单元的每个存储单元中执行码字的解码操作，以产生可靠性信息。 响应于对于至少一个附加的故障存储单元的解码操作失败，所述至少一个附加故障存储单元包括除了解码失败的目标数据存储单元之外的数据和/或奇偶校验存储单元，对于至少一个附加的数据部分的数据部分获得可靠性信息 存储单元故障 从目标数据存储单元以外的存储单元获得的可靠性信息用于生成目标数据存储单元中的数据单元的校正数据。
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公开(公告)号：US20160283111A1
公开(公告)日：2016-09-29
申请号：US14670250
申请日：2015-03-26
Applicant: Intel Corporation
Inventor： Xin Guo , David B. Carlton , Scott Nelson , David J. Pelster , Donia Sebastian
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1626
Abstract: Apparatus, systems, and methods to implement read operations in nonvolatile memory devices are described. In one example, a controller comprises logic to receive a first read request from a host device, place the first read request in a read queue comprising a plurality of read requests directed to the nonvolatile memory, determine a first target die and a first target plane in the nonvolatile memory for the first read request and combine the first read request with at least a second read request in the read queue to form a combined read request, wherein the second read request comprise a second target die, which is the same as the first target die, and a second target plane which is different from the first target plane. Other examples are also disclosed and claimed.
Abstract translation: 描述了在非易失性存储器件中实现读取操作的装置，系统和方法。 在一个示例中，控制器包括从主机设备接收第一读请求的逻辑，将第一读请求置于包括指向非易失性存储器的多个读请求的读队列中，确定第一目标管芯和第一目标平面 在所述非易失性存储器中用于所述第一读取请求，并将所述第一读取请求与所述读取队列中的至少第二读取请求组合以形成组合的读取请求，其中所述第二读取请求包括第二目标模具，其与 第一目标管芯和与第一靶面不同的第二靶平面。 还公开并要求保护其他实例。
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公开(公告)号：US09411683B2
公开(公告)日：2016-08-09
申请号：US14141215
申请日：2013-12-26
Applicant: Intel Corporation
Inventor： Zion S. Kwok , Andre Lei , Scott Nelson
CPC classification number: G06F11/1076 , G06F11/08 , G06F11/1012 , H03M13/1108 , H03M13/1111 , H03M13/3715
Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction codeword retrieved from a memory and apply a first error correction decoder to decode the error correction codeword, wherein the first error correction decoder implements a bit-flipping error correction algorithm which utilizes a variable bit-flipping threshold to determine whether to flip a bit in an error correction codeword. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，存储器控制器包括用于加载从存储器检索的纠错码字的逻辑，并且应用第一纠错解码器来解码纠错码字，其中第一纠错解码器实现位移翻转纠错算法，其使用 可变位跳转阈值，以确定是否在纠错码字中翻转位。 还公开并要求保护其他实施例。
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公开(公告)号：US10176042B2
公开(公告)日：2019-01-08
申请号：US15438655
申请日：2017-02-21
Applicant: INTEL CORPORATION
Inventor： Andre Lei , Scott Nelson , Zion S. Kwok , Ravi H. Motwani
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
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