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公开(公告)号：US20180088652A1
公开(公告)日：2018-03-29
申请号：US15658337
申请日：2017-07-24
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil W. Songer , Rob Gough , David J. Harriman
CPC classification number: G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
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公开(公告)号：US20170168633A1
公开(公告)日：2017-06-15
申请号：US15038795
申请日：2015-06-24
Applicant: INTEL CORPORATION
Inventor： Dong Yeung Kwak , Ramon C. Cancel Olmo , Thomas A. Nugraha , Jue Li , Seh W. Kwa
IPC: G06F3/041 , G02F1/1333 , G06F3/044
CPC classification number: G06F3/0416 , G02B2207/123 , G02F1/13338 , G06F3/0412 , G06F3/044 , G06F21/84
Abstract: Disclosed herein are techniques related to privacy and touch at display devices. The techniques include an apparatus having a touch sensitive electroactive privacy layer of a display device. The touch sensitive electroactive privacy layer is configured to restrict a propagation direction of light emission associated with a display layer of the display device and to register or a touch event. The restriction of propagation is generated by micro louvers formed between privacy layer electrodes in the touch sensitive electroactive privacy layer while the registration of the touch event is detected by mutual capacitance between a touch electrode and one of the privacy layer electrodes.
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公开(公告)号：US10146290B2
公开(公告)日：2018-12-04
申请号：US15658337
申请日：2017-07-24
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil W. Songer , Rob Gough , David J. Harriman
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
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公开(公告)号：US09715269B2
公开(公告)日：2017-07-25
申请号：US14583333
申请日：2014-12-26
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil Songer , Rob Gough , David J. Harriman
CPC classification number: G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
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公开(公告)号：US20150127874A1
公开(公告)日：2015-05-07
申请号：US14583333
申请日：2014-12-26
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil Songer , Rob Gough , David J. Harriman
CPC classification number: G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
Abstract translation: 在一些实施例中，可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备，并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段，而且活动的断言是有利的，因为主机芯片组已经从 降低功耗状态。
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Patent Agency Ranking
公开(公告)号：US10438566B2
公开(公告)日：2019-10-08
申请号：US16145975
申请日：2018-09-28
Applicant: INTEL CORPORATION
Inventor： Seh W. Kwa
Abstract: Various embodiments are generally directed to techniques to partition a display interface such that pixel data associated with display data having indications of an image to be displayed may be transmitted to multiple timing controller and driver (TCON-DR) sets over the display interface without necessitating each TCON-DR set receive all the pixel data. In some examples, the display interface may be partitioned such that each TCON-DR set receives only the pixel data for which the respective TCON-DR set corresponds to.
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公开(公告)号：US09459684B2
公开(公告)日：2016-10-04
申请号：US14101545
申请日：2013-12-10
Applicant: Intel Corporation
Inventor： Robert E. Gough , Seh W. Kwa , Neil W. Songer , Jaya L. Jeyaseelan , Barnes Cooper
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3215 , G06F1/3228
Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
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公开(公告)号：US09116697B2
公开(公告)日：2015-08-25
申请号：US14141536
申请日：2013-12-27
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Michael Calyer , Ravi Ranganathan , Narayan Biswal
CPC classification number: G06F1/3218 , G06F1/3265 , G09G3/3611 , G09G5/36 , G09G2330/022
Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.
Abstract translation: 描述技术来监视图形处理活动的水平，并基于该级别来控制功率使用。 当在一段时间内未检测到图形处理活动时，指示用于显示装置的定时控制器捕获当前图像并重复显示所捕获的图像。 图形处理设备可以关闭电源。 当检测到图形处理活动时，图形处理设备通电，用于捕获图像并显示捕获的图像的组件断电。
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公开(公告)号：US09110665B2
公开(公告)日：2015-08-18
申请号：US14141533
申请日：2013-12-27
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Michael Calyer , Ravi Ranganathan , Narayan Biswal
CPC classification number: G06F1/3218 , G06F1/3265 , G09G3/3611 , G09G5/36 , G09G2330/022
Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.
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公开(公告)号：US11276373B2
公开(公告)日：2022-03-15
申请号：US17030758
申请日：2020-09-24
Applicant: INTEL CORPORATION
Inventor： Seh W. Kwa
Abstract: Various embodiments are generally directed to techniques to partition a display interface such that pixel data associated with display data having indications of an image to be displayed may be transmitted to multiple timing controller and driver (TCON-DR) sets over the display interface without necessitating each TCON-DR set receive all the pixel data. In some examples, the display interface may be partitioned such that each TCON-DR set receives only the pixel data for which the respective TCON-DR set corresponds to.
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