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1.发明申请公开(公告)号：US20190101972A1
公开(公告)日：2019-04-04
申请号：US15721772
申请日：2017-09-30
Applicant: Intel Corporation
Inventor： Vasudev Bibikar , Aswin Ramachandran , Chin Seng Lu , Moorthy Rajesh , Darren S. Crews
Abstract: A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.
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2.发明授权公开(公告)号：US11314299B2
公开(公告)日：2022-04-26
申请号：US16832012
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： Patrick Kam-Shing Leung , Ashraf H. Wadaa , Trevor S. Love , Vasudev Bibikar
IPC: G06F1/26
Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.
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公开(公告)号：US09961478B2
公开(公告)日：2018-05-01
申请号：US14450482
申请日：2014-08-04
Applicant: Intel Corporation
Inventor： David W. Browning , Kristoffer D. Fleming , Robert E. Gough , Guy G. Sotomayor , Vasudev Bibikar , Ankush Varma
Abstract: The present disclosure is directed to logging random “chirps” of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.
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4.发明授权Techniques for putting platform subsystems into a lower power state in parallel 有权将平台子系统并入较低功率状态的技术公开(公告)号：US09471132B2
公开(公告)日：2016-10-18
申请号：US14040156
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Vasudev Bibikar , Rajith K. Mavila
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
Abstract translation: 各种实施例通常涉及用于确定具有用于进入较低功率状态的相关联的子系统睡眠控制寄存器的多个子系统中的每一个的睡眠配置状态的装置，方法和其他技术，配置每个相关联的子系统睡眠控制寄存器 具有每个子系统的睡眠配置状态，并且当转换到较低功率状态时并行地启用每个子系统的睡眠配置状态。
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公开(公告)号：US20160267883A1
公开(公告)日：2016-09-15
申请号：US14644767
申请日：2015-03-11
Applicant: Intel Corporation
Inventor： Vasudev Bibikar , Rajesh Poornachandran , Ajaya V. Durg , Arpit Shah , Anil K. Sabbavarapu , Nabil F. Kerkiz , Quang T. Le , Ryan R. Pinto , Moorthy Rajesh , James A. Bish , Ranjani Sridharan
CPC classification number: G09G5/36 , G09G5/39 , G09G5/395 , G09G2320/103 , G09G2330/021 , G09G2360/121 , G09G2360/125
Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.
Abstract translation: 用于低功率显示刷新待机的技术包括具有诸如LCD面板的显示器的计算设备。 计算设备可以包括具有处理器，I / O子系统，显示控制器和存储器的片上系统（SoC）。 当计算设备确定显示图像是静态时，计算设备进入低功率显示刷新待机模式，为诸如处理器核心，外围设备和专用显示缓冲器之外的存储器的SoC的不需要的组件供电。 显示控制器可以通过I / O子系统访问专用显示缓冲区，并将图像输出到显示器。 当显示控制器FIFO充满图像数据时，计算设备可能会关闭I / O子系统和专用显示缓冲区，并周期性地打开I / O子系统和显示缓冲区以填充显示控制器FIFO。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US10060966B2
公开(公告)日：2018-08-28
申请号：US14667365
申请日：2015-03-24
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar
CPC classification number: G01R31/2637 , G01R31/2856 , G06F1/3203 , H01L22/34 , H01L23/58
Abstract: A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using “in situ,” or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.
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公开(公告)号：US09784791B2
公开(公告)日：2017-10-10
申请号：US14335066
申请日：2014-07-18
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar , P. Reddy Sahajananda , Sunghyun Koh , Naveendran Balasingam
IPC: G01R31/317 , G01R31/3177 , G01R31/02 , G01R31/40 , G05F1/10
CPC classification number: G01R31/31725 , G01R31/025 , G01R31/40 , G05F1/10
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
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公开(公告)号：US11686780B2
公开(公告)日：2023-06-27
申请号：US17232018
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar , P. Reddy Sahajananda , Sunghyun Koh , Naveendran Balasingam
IPC: G01R31/40 , G05F1/10 , G01R31/317
CPC classification number: G01R31/40 , G05F1/10 , G01R31/31725
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
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公开(公告)号：US20210231746A1
公开(公告)日：2021-07-29
申请号：US17232018
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar , P. Reddy Sahajananda , Sunghyun Koh , Naveendran Balasingam
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
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公开(公告)号：US09620088B2
公开(公告)日：2017-04-11
申请号：US14644767
申请日：2015-03-11
Applicant: Intel Corporation
Inventor： Vasudev Bibikar , Rajesh Poornachandran , Ajaya V. Durg , Arpit Shah , Anil K. Sabbavarapu , Nabil F. Kerkiz , Quang T. Le , Ryan R. Pinto , Moorthy Rajesh , James A. Bish , Ranjani Sridharan
CPC classification number: G09G5/36 , G09G5/39 , G09G5/395 , G09G2320/103 , G09G2330/021 , G09G2360/121 , G09G2360/125
Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.
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