公开(公告)号：US11621045B2

公开(公告)日：2023-04-04

申请号：US16808955

申请日：2020-03-04

Applicant: Intel Corporation

Inventor： Xiang Yang

IPC: G11C16/34 ,  G06F3/06 ,  G11C16/04

Abstract: An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction.

公开(公告)号：US20220310178A1

公开(公告)日：2022-09-29

申请号：US17213150

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/10

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

公开(公告)号：US11004524B2

公开(公告)日：2021-05-11

申请号：US16591978

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Shantanu R. Rajwade ,  Ali Khakifirooz ,  Tarek Ahmed Ameen Beshari

IPC: G11C11/00 ,  G11C16/34 ,  G11C16/08

Abstract: An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.

公开(公告)号：US12224019B2

公开(公告)日：2025-02-11

申请号：US17213150

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/00 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

公开(公告)号：US20210257036A1

公开(公告)日：2021-08-19

申请号：US16790074

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Tarek Ahmed Ameen Beshari ,  Narayanan Ramanan ,  Arun Thathachary ,  Shantanu Rajwade ,  Matin Amani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

公开(公告)号：US11094386B1

公开(公告)日：2021-08-17

申请号：US16790074

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Tarek Ahmed Ameen Beshari ,  Narayanan Ramanan ,  Arun Thathachary ,  Shantanu Rajwade ,  Matin Amani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C11/419

Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

公开(公告)号：US11056203B1

公开(公告)日：2021-07-06

申请号：US16788194

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Xiang Yang ,  Pranav Kalavade ,  Ali Khakifirooz ,  Shantanu R. Rajwade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.