公开(公告)号：US20230328947A1

公开(公告)日：2023-10-12

申请号：US18209988

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Zheng GUO ,  Clifford L. ONG ,  Eric A. KARL ,  Mark T. BOHR

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

公开(公告)号：US20230317148A1

公开(公告)日：2023-10-05

申请号：US17710942

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Clifford ONG ,  Leonard P. GULER ,  Smita SHRIDHARAN ,  Zheng GUO ,  Charles H. WALLACE ,  Eric A. KARL ,  Mauro J. KOBRINSKY ,  Shem O. OGADHOH ,  Tahir GHANI

IPC: G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098682A1

公开(公告)日：2020-03-26

申请号：US16604807

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L23/535

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20230223339A1

公开(公告)日：2023-07-13

申请号：US18119225

申请日：2023-03-08

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L23/535 ,  H10B10/12 ,  H01L27/0924

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20200058656A1

公开(公告)日：2020-02-20

申请号：US16605903

申请日：2017-06-22

Applicant: Intel Corporation

Inventor： Zheng GUO ,  Clifford L. ONG ,  Eric A. KARL ,  Mark T. BOHR

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

公开(公告)号：US20170011793A1

公开(公告)日：2017-01-12

申请号：US15115464

申请日：2014-03-05

Applicant: INTEL CORPORATION

Inventor： Gururaj K. SHAMANNA ,  Stefan RUSU ,  Eric A. KARL ,  Zheng GUO

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract translation: 描述了一种装置，包括：存储器; 第一电源节点，用于接收第一电源; 耦合到所述存储器以向所述存储器提供第二电源的第二电源节点; 耦合到所述第一和第二电源节点的电路，所述电路可操作以通过自适应地调整写入辅助脉冲的信号特性来动态地调制所述第二电源中的下降。

公开(公告)号：US20250125259A1

公开(公告)日：2025-04-17

申请号：US18999916

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L23/535 ,  H10B10/00 ,  H10D84/85

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20250071963A1

公开(公告)日：2025-02-27

申请号：US18946106

申请日：2024-11-13

Applicant: Intel Corporation

Inventor： Zheng GUO ,  Clifford L. ONG ,  Eric A. KARL ,  Mark T. BOHR

IPC: H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

公开(公告)号：US20240213154A1

公开(公告)日：2024-06-27

申请号：US18599049

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/0924 ,  H10B10/12

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20230317612A1

公开(公告)日：2023-10-05

申请号：US17710867

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Clifford ONG ,  Zheng GUO ,  Eirc A. KARL ,  Smita SHRIDHARAN ,  Mauro J. KOBRINSKY ,  Shem O. OGADHOH ,  Clifford J. ENGEL ,  Charles H. WALLACE ,  Leonard P. GULER

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L27/1104 ,  H01L27/092 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/1108

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.