公开(公告)号：US20230317612A1

公开(公告)日：2023-10-05

申请号：US17710867

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Clifford ONG ,  Zheng GUO ,  Eirc A. KARL ,  Smita SHRIDHARAN ,  Mauro J. KOBRINSKY ,  Shem O. OGADHOH ,  Clifford J. ENGEL ,  Charles H. WALLACE ,  Leonard P. GULER

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L27/1104 ,  H01L27/092 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/1108

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

公开(公告)号：US20210358713A1

公开(公告)日：2021-11-18

申请号：US17388945

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US20210098373A1

公开(公告)日：2021-04-01

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan G. ALZATE VINASCO ,  Chieh-Jen KU ,  Shem O. OGADHOH ,  Allen B. GARDINER ,  Blake C. LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US20210125992A1

公开(公告)日：2021-04-29

申请号：US16645362

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Shem O. OGADHOH ,  Yih WANG ,  Bernhard SELL ,  Allen GARDINER ,  Blake LIN ,  Juan G. ALZATE VINASCO ,  Pei-Hua WANG ,  Chieh-Jen KU ,  Abhishek A. SHARMA

IPC: H01L27/108 ,  H01L27/12

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317148A1

公开(公告)日：2023-10-05

申请号：US17710942

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Clifford ONG ,  Leonard P. GULER ,  Smita SHRIDHARAN ,  Zheng GUO ,  Charles H. WALLACE ,  Eric A. KARL ,  Mauro J. KOBRINSKY ,  Shem O. OGADHOH ,  Tahir GHANI

IPC: G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20190164723A1

公开(公告)日：2019-05-30

申请号：US16323128

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

IPC: H01J37/30 ,  H01L21/033 ,  H01J37/317

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.