公开(公告)号：US20160358304A1

公开(公告)日：2016-12-08

申请号：US14778508

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Zhi WANG ,  Yao Zu DONG

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F7/00 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/3636 ,  G06F11/3644 ,  G06T1/60

Abstract: Embodiments of graphics instruction instrumentor (“GII”) and a graphics profiler (“GP”) are described. The GII may facilitate profiling of execution of graphics instructions by one or more graphics processors. The GII may identify target graphics instructions for which execution profile information is desired. The GII may store instrumentation graphics instructions in a graphics instruction buffer. The instrumentation graphics instructions may facilitate the GP in collecting graphics profile information. For example, timestamp-storage instructions may be store timestamps before and after execution of the target graphics instructions. The GII also may store an interrupt-generation instruction to cause an interrupt to be sent to the GP so that the GP may begin collection of graphics profile data. The GII may store an event-wait instruction to pause the graphics processors until an event is received. Other embodiments may be described and claimed.

Abstract translation: 描述了图形指令工具（“GII”）和图形分析器（“GP”）的实施例。 GII可以促进由一个或多个图形处理器执行图形指令的分析。 GII可以识别期望执行简档信息的目标图形指令。 仪表图形指令可以在图形指令缓冲器中存储。 仪器图形指令可能有助于GP收集图形配置文件信息。 例如，时间戳存储指令可以在执行目标图形指令之前和之后存储时间戳。 GII还可以存储中断生成指令以使中断发送到GP，以便GP可以开始收集图形配置文件数据。 GII可以存储事件等待指令来暂停图形处理器直到接收到事件。 可以描述和要求保护其他实施例。

公开(公告)号：US20210264559A1

公开(公告)日：2021-08-26

申请号：US17256203

申请日：2018-11-30

Applicant: INTEL CORPORATION

Inventor： Matthew ROPER ,  Zhi WANG ,  Satyeshwar SINGH ,  Kalyan KONDAPALLY ,  Daniel VETTER ,  Wei ZHANG

IPC: G06T1/20 ,  G06F9/455 ,  G06T1/60

Abstract: Apparatus and method for Implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises host execution circuitry to execute instructions to implement a host and virtualization instructions to implement a virtualized execution environment comprising a plurality of virtual machines (VMs); graphics execution circuitry to execute graphics instructions to render framebuffers on behalf of each VM, each framebuffer associated with a virtual function (VF); and a display engine comprising one or more display pipes and a plurality of display planes; wherein a dynamic mapping is to be performed to associate one or more of the framebuffers to one or more of the display planes, the dynamic mapping comprising generating a framebuffer object with framebuffer information required by a physical function (PF) of the host to update the one or more display planes.

公开(公告)号：US20210263755A1

公开(公告)日：2021-08-26

申请号：US17256204

申请日：2018-11-30

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Ankur SHAH ,  David COWPERTHWAITE ,  Zhi WANG ,  Zhenyu WANG ,  Kalyan KONDAPALLY ,  Jonathan BLOOMFIELD ,  Wei ZHANG

IPC: G06F9/451 ,  G06F9/455 ,  G06F9/4401 ,  G06F3/14 ,  G09G5/00

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

公开(公告)号：US20180122039A1

公开(公告)日：2018-05-03

申请号：US15553143

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Zhi WANG

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48 ,  G06F12/1027 ,  G06F12/1009 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F8/427 ,  G06F8/44 ,  G06F9/45512 ,  G06F9/45558 ,  G06F9/4843 ,  G06F9/4881 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/302 ,  G06F2212/657 ,  G06T1/60 ,  G06T15/005

Abstract: An apparatus may include a graphics processing unit (GPU) and a hypervisor. The hypervisor may include a command parser to parse graphics memory addresses associated with a workload of a virtual machine of the apparatus, and generate a first shadow global graphics translation table (SGGT) for translating the graphics memory addresses. The hypervisor may further include a GPU scheduler to check conflict between the first SGGTT and a second SGGTT containing graphics memory addresses used by working sets being-executed or to-be-executed by the render engines of the GPU, and schedule the workload of the virtual machine to a render engine when there is no conflict between the first SGGTT and the second SGGTT. Other embodiments may be described and/or claimed.

公开(公告)号：US20220188965A1

公开(公告)日：2022-06-16

申请号：US17598267

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Weinan LI ,  Yan ZHAO ,  Zhi WANG ,  Wei ZHANG

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/50

Abstract: An apparatus and method for scheduling workloads across virtualized graphics processors. For example, one embodiment of a graphics processing apparatus comprises first graphics processing resources to process graphics commands and execute graphics data; workload scheduling circuitry to schedule workloads for execution on the first graphics processing resources; and workload queuing circuitry to implement a local queue to store local workload entries, each local workload entry associated with a locally-submitted workload and an external workload queue to store external workload entries, each external workload entry associated with an externally-submitted workload submitted for execution by an external graphics processing apparatus, in one embodiment, the workload scheduling circuitry schedules the locally-submitted workloads identified in the local queue and externally-submitted workloads identified in the external workload queue for processing by specified portions of the first graphics processing resources.