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    DITHERING FOR SPUR REDUCTION IN LOCAL OSCILLATOR GENERATION
    1.
    发明申请
    DITHERING FOR SPUR REDUCTION IN LOCAL OSCILLATOR GENERATION 审中-公开

    公开(公告)号：US20200280318A1

    公开(公告)日：2020-09-03

    申请号：US16646746

    申请日：2017-09-12

    Applicant: INTEL IP CORPORATION

    Inventor： Christoph S. Preissi ,  Peter Preyler ,  Thomas Mayer

    IPC: H03L7/081 ,  H03L7/07 ,  H03L7/16 ,  G06F1/025

    Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

    Dithering for spur reduction in local oscillator generation
    2.
    发明授权
    Dithering for spur reduction in local oscillator generation 有权

    公开(公告)号：US10979056B2

    公开(公告)日：2021-04-13

    申请号：US16646746

    申请日：2017-09-12

    Applicant: INTEL IP CORPORATION

    Inventor： Christoph S. Preissel ,  Peter Preyler ,  Thomas Mayer

    IPC: H03L7/081 ,  G06F1/025 ,  H03L7/07 ,  H03L7/16

    Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

    System and a method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop
    3.
    发明授权
    System and a method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop 有权

    公开(公告)号：US10298243B2

    公开(公告)日：2019-05-21

    申请号：US15575830

    申请日：2016-06-08

    Applicant: Intel IP Corporation

    Inventor： Thomas Mayer

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091 ,  H04B1/02

    Abstract: A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

    Phase tracker for a phase locked loop
    4.
    发明授权
    Phase tracker for a phase locked loop 有权
    相位跟踪器用于锁相环

    公开(公告)号：US09584139B2

    公开(公告)日：2017-02-28

    申请号：US14494718

    申请日：2014-09-24

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Thomas Mayer ,  Andreas Mayer ,  Thorsten Tracht

    IPC: H03L7/08 ,  H03L7/085 ,  G04F10/00 ,  H03L7/197

    CPC classification number: H03L7/085 ,  G04F10/005 ,  H03L7/1976

    Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

    Abstract translation: 锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。 锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。 反馈信号被提供给前馈路径。 锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值 该输出信号由于锁相环中的锁定状态而中断。

    Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for obtaining calibration data and a method for generating a local oscillator signal
    5.
    发明授权
    Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for obtaining calibration data and a method for generating a local oscillator signal 有权
    电路，集成电路，发送器，接收器，收发器，用于获得校准数据的方法以及用于产生本地振荡器信号的方法

    公开(公告)号：US09537585B2

    公开(公告)日：2017-01-03

    申请号：US14620488

    申请日：2015-02-12

    Applicant: Intel IP Corporation

    Inventor： Thomas Mayer ,  Stefan Tertinek ,  Peter Preyler

    IPC: H04B17/21 ,  H04B1/62 ,  H03L7/197

    CPC classification number: H04B17/21 ,  H03L7/1976 ,  H04B1/62

    Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.

    Abstract translation: 根据示例的电路包括数字 - 时间转换器和耦合到数字 - 时间转换器并被配置为产生从提供给信号处理电路的信号导出的处理信号的信号处理电路，处理信号包括 相对于提供给信号处理电路的信号的预定相位关系，其中电路被配置为接收参考信号并且基于接收到的参考信号产生输出信号。 测量电路被配置为测量输出信号和参考信号之间的延迟，其中数字 - 时间转换器的输出耦合到存储器，该存储器被配置为存储数字 - 时间转换器的校准数据，基于 测量延迟。

    SYNCHRONIZING A DIGITAL FREQUENCY SHIFT
    9.
    发明申请
    SYNCHRONIZING A DIGITAL FREQUENCY SHIFT 审中-公开

    公开(公告)号：US20200059386A1

    公开(公告)日：2020-02-20

    申请号：US16492801

    申请日：2017-04-01

    Applicant: Intel IP Corporation

    Inventor： Christian Mayer ,  Thomas Mayer

    IPC: H04L27/00 ,  H04L27/227 ,  H03D3/00 ,  H04L27/26

    Abstract: An apparatus and a method for synchronizing a Digital Frequency Shift (DFS) for a signal to be transmitted over a wireless channel are disclosed. For example, the method, by a synchronizer, transmits a DFS trigger to a Digital Front End (DFE) processor and a Local Oscillator (LO) trigger to an LO in a synchronous manner, the method, by the DFE processor, applies a DFS on received data in response to receiving the DFS trigger, the method, by the LO, applies a complementary shift on a carrier signal in response to receiving the LO trigger, the method, by the upconverter, digital-to-analog converts and radio frequency modulates the digital frequency-shifted received data and the complementary-shifted carrier signal. In another example, the method, by the synchronizer, transmits a phase error to a phase error corrector that performs a phase error correction.

    SYSTEM AND A METHOD FOR DETERMINING A CORRECTION FOR AN OUTPUT VALUE OF A TIME-TO-DIGITAL CONVERTER WITHIN A PHASE-LOCKED LOOP
    10.
    发明申请
    SYSTEM AND A METHOD FOR DETERMINING A CORRECTION FOR AN OUTPUT VALUE OF A TIME-TO-DIGITAL CONVERTER WITHIN A PHASE-LOCKED LOOP 审中-公开

    公开(公告)号：US20180131380A1

    公开(公告)日：2018-05-10

    申请号：US15575830

    申请日：2016-06-08

    Applicant: Intel IP Corporation

    Inventor： Thomas Mayer

    IPC: H03L7/099 ,  H03L7/091

    CPC classification number: H03L7/0992 ,  H03L7/091 ,  H03L7/197 ,  H04B1/02

    Abstract: A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

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