公开(公告)号：US09659820B2

公开(公告)日：2017-05-23

申请号：US15143969

申请日：2016-05-02

Applicant: International Business Machines Corporation ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US20150279780A1

公开(公告)日：2015-10-01

申请号：US14314945

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen SPOONER ,  Nicole A. SAULNIER

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US10551254B2

公开(公告)日：2020-02-04

申请号：US15927224

申请日：2018-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chandrasekara Kothandaraman ,  Sami Rosenblatt ,  Akil K. Sutton

IPC: G01L1/00 ,  G01L1/14 ,  H03K3/03 ,  H03K5/26 ,  H01L29/78 ,  H01L23/48

Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

公开(公告)号：US20160247722A1

公开(公告)日：2016-08-25

申请号：US15143969

申请日：2016-05-02

Applicant: International Business Machines Corporation ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US20170356811A1

公开(公告)日：2017-12-14

申请号：US15182450

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chandrasekara Kothandaraman ,  Sami Rosenblatt ,  Akil K. Sutton

IPC: G01L1/14 ,  H03K3/03 ,  H01L29/78 ,  H01L23/48 ,  H03K5/26

CPC classification number: G01L1/14 ,  G01R31/2642 ,  H01L23/481 ,  H01L29/7842 ,  H03K3/0315 ,  H03K5/26

Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

公开(公告)号：US09391020B2

公开(公告)日：2016-07-12

申请号：US14314945

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US20180217012A1

公开(公告)日：2018-08-02

申请号：US15927224

申请日：2018-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chandrasekara Kothandaraman ,  Sami Rosenblatt ,  Akil K. Sutton

IPC: G01L1/14 ,  H01L29/78 ,  H01L23/48 ,  H03K3/03 ,  H03K5/26

CPC classification number: G01L1/14 ,  G01R31/2831 ,  G01R31/2856 ,  G01R31/2874 ,  H01L23/481 ,  H01L29/7842 ,  H03K3/0315 ,  H03K5/26

Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

公开(公告)号：US09970830B2

公开(公告)日：2018-05-15

申请号：US15182450

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chandrasekara Kothandaraman ,  Sami Rosenblatt ,  Akil K. Sutton

IPC: G01L1/00 ,  G01L1/14 ,  H03K3/03 ,  H03K5/26 ,  H01L23/48 ,  H01L29/78

CPC classification number: G01L1/14 ,  G01R31/2642 ,  H01L23/481 ,  H01L29/7842 ,  H03K3/0315 ,  H03K5/26

Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

公开(公告)号：US20140184242A1

公开(公告)日：2014-07-03

申请号：US13732474

申请日：2013-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Erik L. Hedberg ,  Daeik D. Kim ,  Dallas M. Lea ,  Akil K. Sutton ,  Steven J. Zier

IPC: G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2625

Abstract: A method and apparatus measure transistor bandwidth of a device under test in-line and on-wafer. The method includes disposing a measurement circuit on a chip within a wafer, the measurement circuit including a ring oscillator generating an oscillation frequency for transition through the device under test on the wafer, and obtaining an amplitude gain based on the measurement circuit for the corresponding frequency.

Abstract translation: 一种测量在线和晶圆上的器件的晶体管带宽的方法和装置。 该方法包括将测量电路设置在晶片内的芯片上，测量电路包括产生振荡频率的环形振荡器，用于在晶片上转变通过被测器件，并且基于相应频率的测量电路获得幅度增益 。