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公开(公告)号：US10896059B2
公开(公告)日：2021-01-19
申请号：US15457801
申请日：2017-03-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Wesley M. Felter , Alexandre P. Ferreira , Karthick Rajamani , Juan C. Rubio , Cong Xu
IPC: G06F9/50 , G06F12/0842
Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.
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公开(公告)号：US20150143020A1
公开(公告)日：2015-05-21
申请号：US14082624
申请日：2013-11-18
Applicant: International Business Machines Corporation
Inventor： Alexandre P. Ferreira , Jente B. Kuang , Janani Mukundan , Karthick Rajamani
CPC classification number: G11C8/12 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
Abstract translation: 提供了一种存储器，其包括被配置成多个小金库的一组非易失性存储器单元。 可以独立且独立于非易失性存储单元组中的其他小金库启用多个小组中的每个小钞。 存储器还包括耦合到非易失性存储器阵列的存储体组合的外围电路组电路，其被配置为使能在所述多个小组内的所选小组内的位线的选定子集。 此外，存储器包括耦合到外围小金属电路的小金库选择电路，其被配置为选择与所选择的小金库相关联的数据，以从该小钞中读出或写入该小钞。
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公开(公告)号：US09135577B2
公开(公告)日：2015-09-15
申请号：US13648441
申请日：2012-10-10
Applicant: International Business Machines Corporation
Inventor： Wael R. El-Essawy , Alexandre P. Ferreira , Thomas W. Keller, Jr. , Sani R. Nassif , Karthick Rajamani , Juan C. Rubio
Abstract: A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold.
Abstract translation: 提供了一种用于基于电路中的信号检测来统计确定电力电路连接性的机制。 收集来自电路的信号数据，并且使用所收集的信号数据的统计分析来确定来自电路的所收集的信号数据中是否存在感兴趣的信号。 统计分析包括在预定时间段内使用平均电流值和信号数据的当前值的统计偏差来计算置信区间。 将置信区间与第一阈值和第二阈值进行比较。 确定响应于高于第一阈值的置信区间存在信号。 响应于置信范围低于第二阈值，确定该信号不存在。
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Patent Agency Ranking
公开(公告)号：US20140136786A1
公开(公告)日：2014-05-15
申请号：US13675546
申请日：2012-11-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Gary D. Carpenter , Stefanie R. Chiras , Alexandre P. Ferreira , Jente B. Kuang , Karthick Rajamani , Freeman L. Rawson, III
IPC: G06F12/08
CPC classification number: G06F9/466 , G06F12/1416 , G06F13/00
Abstract: A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.
Abstract translation: 处理器包括处理器核心，高速缓存和跟踪器。 处理器核心被配置为执行持久写入指令并接收完成的持久写入指令的通知。 跟踪器被配置为跟踪持久写入指令的完成状态。
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公开(公告)号：US20180260330A1
公开(公告)日：2018-09-13
申请号：US15457801
申请日：2017-03-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Wesley M. Felter , Alexandre P. Ferreira , Karthick Rajamani , Juan C. Rubio , Cong Xu
IPC: G06F12/0871 , G06F12/0811 , G06F12/0831
CPC classification number: G06F9/50 , G06F12/0842 , G06F2212/604
Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.
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公开(公告)号：US09286959B2
公开(公告)日：2016-03-15
申请号：US14082624
申请日：2013-11-18
Applicant: International Business Machines Corporation
Inventor： Alexandre P. Ferreira , Jente B. Kuang , Janani Mukundan , Karthick Rajamani
CPC classification number: G11C8/12 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
Abstract translation: 提供了一种存储器，其包括被配置成多个小金库的一组非易失性存储器单元。 可以独立且独立于非易失性存储单元组中的其他小金库启用多个小组中的每个小钞。 存储器还包括耦合到非易失性存储器阵列的存储体组合的外围电路组电路，其被配置为使能在所述多个小组内的所选小组内的位线的选定子集。 此外，存储器包括耦合到外围小金属电路的小金库选择电路，其被配置为选择与所选择的小金库相关联的数据，以从该小钞中读出或写入该小钞。
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公开(公告)号：US09081606B2
公开(公告)日：2015-07-14
申请号：US13675546
申请日：2012-11-13
Applicant: International Business Machines Corporation
Inventor： Gary D. Carpenter , Stefanie R. Chiras , Alexandre P. Ferreira , Jente B. Kuang , Karthick Rajamani , Freeman L. Rawson, III
CPC classification number: G06F9/466 , G06F12/1416 , G06F13/00
Abstract: A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.
Abstract translation: 处理器包括处理器核心，高速缓存和跟踪器。 处理器核心被配置为执行持久写入指令并接收完成的持久写入指令的通知。 跟踪器被配置为跟踪持久写入指令的完成状态。
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公开(公告)号：US20140100804A1
公开(公告)日：2014-04-10
申请号：US13648441
申请日：2012-10-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Wael R. El-Essawy , Alexandre P. Ferreira , Thomas W. Keller, JR. , Sani R. Nassif , Karthick Rajamani , Juan C. Rubio
IPC: G06F17/18
Abstract: A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold.
Abstract translation: 提供了一种用于基于电路中的信号检测来统计确定电力电路连接性的机制。 收集来自电路的信号数据，并且使用所收集的信号数据的统计分析来确定来自电路的所收集的信号数据中是否存在感兴趣的信号。 统计分析包括在预定时间段内使用平均电流值和信号数据的当前值的统计偏差来计算置信区间。 将置信区间与第一阈值和第二阈值进行比较。 确定响应于高于第一阈值的置信区间存在信号。 响应于置信范围低于第二阈值，确定该信号不存在。
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