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    Gate stacks with multiple high-κ dielectric layers
    1.
    发明授权
    Gate stacks with multiple high-κ dielectric layers 有权

    公开(公告)号：US11961895B2

    公开(公告)日：2024-04-16

    申请号：US17447109

    申请日：2021-09-08

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Ravikumar Ramachandran ,  Barry Linder ,  Shahab Siddiqui ,  Elnatan Mataev

    IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51

    CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/513 ,  H01L29/517

    Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

    GATE STACKS WITH MULTIPLE HIGH-K DIELECTRIC LAYERS
    2.
    发明申请
    GATE STACKS WITH MULTIPLE HIGH-K DIELECTRIC LAYERS 有权

    公开(公告)号：US20230075740A1

    公开(公告)日：2023-03-09

    申请号：US17447109

    申请日：2021-09-08

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Ravikumar Ramachandran ,  Barry Linder ,  Shahab Siddiqui ,  Elnatan Mataev

    IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51

    Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

    RRAM STRUCTURES IN THE BEOL
    3.
    发明申请
    RRAM STRUCTURES IN THE BEOL 有权

    公开(公告)号：US20210280638A1

    公开(公告)日：2021-09-09

    申请号：US16813166

    申请日：2020-03-09

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Barry Linder ,  Vijay Narayanan

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

    SWITCHABLE METAL INSULATOR METAL CAPACITOR
    4.
    发明申请
    SWITCHABLE METAL INSULATOR METAL CAPACITOR 有权

    公开(公告)号：US20210036096A1

    公开(公告)日：2021-02-04

    申请号：US16527830

    申请日：2019-07-31

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Andrew Tae Kim ,  Barry Linder

    IPC: H01L49/02 ,  H01L45/00

    Abstract: A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.

    FABRICATION OF PHASE CHANGE MEMORY CELL IN INTEGRATED CIRCUIT
    5.
    发明申请
    FABRICATION OF PHASE CHANGE MEMORY CELL IN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200295261A1

    公开(公告)日：2020-09-17

    申请号：US16299313

    申请日：2019-03-12

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Andrew Tae Kim ,  Barry Linder

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

    RRAM structures in the BEOL
    8.
    发明授权
    RRAM structures in the BEOL 有权

    公开(公告)号：US11877458B2

    公开(公告)日：2024-01-16

    申请号：US16813166

    申请日：2020-03-09

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Barry Linder ,  Vijay Narayanan

    IPC: H01L45/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00 ,  G06N3/04 ,  G06N3/063

    CPC classification number: H10B63/80 ,  H10N70/066 ,  H10N70/24 ,  H10N70/841 ,  H10N70/8833 ,  G06N3/04 ,  G06N3/063

    Abstract: A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

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