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公开(公告)号：US10574240B2
公开(公告)日：2020-02-25
申请号：US15445587
申请日：2017-02-28
Applicant: International Business Machines Corporation
Inventor： Keith A. Jenkins , Peilin Song , James H. Stathis , Franco Stellari
Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.
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公开(公告)号：US10360526B2
公开(公告)日：2019-07-23
申请号：US15221185
申请日：2016-07-27
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Karthik Balakrishnan , Keith A. Jenkins , Barry P. Linder
Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.
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公开(公告)号：US10102090B2
公开(公告)日：2018-10-16
申请号：US15156136
申请日：2016-05-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/00 , G06F11/22 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.
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公开(公告)号：US09952274B2
公开(公告)日：2018-04-24
申请号：US14657437
申请日：2015-03-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder
CPC classification number: G01R31/2628 , G01R31/025 , G01R31/2601 , G01R31/2648
Abstract: A method of measuring semiconductor output characteristics is provided that includes connecting a pulse generator to the gate structure of a semiconductor device, and applying a plurality of voltage pulses at least some of which having a different pulse width to the gate structure of the semiconductor device. The average current is measured from the drain structure of the device for a duration of each pulse of the plurality of pulses. From the measured values for the average current, a self-heating curve of the average current divided by the pulse width is plotted as a function of the pulse width. The self-heating curve is then extrapolated to a pulse width substantially equal to zero to provide a value of drain current measurements without self-heating effects.
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公开(公告)号：US20180038906A1
公开(公告)日：2018-02-08
申请号：US15230067
申请日：2016-08-05
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Chen-Yong Cher , Keith A. Jenkins , Barry P. Linder
IPC: G01R31/28
Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.
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Patent Agency Ranking
公开(公告)号：US09863994B2
公开(公告)日：2018-01-09
申请号：US15060497
申请日：2016-03-03
Applicant: International Business Machines Corporation
Inventor： Chen-Yong Cher , Keith A. Jenkins , Barry P. Linder
IPC: G01R31/02 , G01R19/165
CPC classification number: G01R31/025 , G01R19/165 , G01R31/2884 , G01R31/3008
Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.
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公开(公告)号：US20170350928A1
公开(公告)日：2017-12-07
申请号：US15684181
申请日：2017-08-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins
IPC: G01R29/02 , H03K5/13 , H03K5/133 , G01R29/027 , H03K5/00
Abstract: Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.
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公开(公告)号：US09829535B2
公开(公告)日：2017-11-28
申请号：US15001373
申请日：2016-01-20
Applicant: International Business Machines Corporation
Inventor： Karthik Balakrishnan , Bruce M. Fleischer , Keith A. Jenkins , Christos Vezyrtzis
IPC: G01R31/28 , G01R31/317
CPC classification number: G01R31/2884 , G01R31/31726
Abstract: An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.
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公开(公告)号：US09791500B2
公开(公告)日：2017-10-17
申请号：US14742906
申请日：2015-06-18
Applicant: International Business Machines Corporation
Inventor： Keith A. Jenkins , Barry P. Linder , Kevin G. Stawiasz
CPC classification number: G01R31/2853 , G01R31/026 , G01R31/2856 , G01R31/2858 , G06F11/00 , H01L22/34
Abstract: A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.
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公开(公告)号：US09678141B2
公开(公告)日：2017-06-13
申请号：US14747546
申请日：2015-06-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder
CPC classification number: G01R31/2628 , G01R31/025 , G01R31/2601 , G01R31/2648
Abstract: A method of measuring semiconductor output characteristics is provided that includes connecting a pulse generator to the gate structure of a semiconductor device, and applying a plurality of voltage pulses at least some of which having a different pulse width to the gate structure of the semiconductor device. The average current is measured from the drain structure of the device for a duration of each pulse of the plurality of pulses. From the measured values for the average current, a self-heating curve of the average current divided by the pulse width is plotted as a function of the pulse width. The self-heating curve is then extrapolated to a pulse width substantially equal to zero to provide a value of drain current measurements without self-heating effects.
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