公开(公告)号：US20230197603A1

公开(公告)日：2023-06-22

申请号：US17645402

申请日：2021-12-21

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung CHEN ,  Su Chen FAN ,  Dechao GUO ,  Carl RADENS ,  Indira SESHADRI

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76877

Abstract: An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

公开(公告)号：US20230178547A1

公开(公告)日：2023-06-08

申请号：US17457588

申请日：2021-12-03

Applicant: International Business Machines Corporation

Inventor： Maruf Amin BHUIYAN ,  Ardasheir RAHMAN ,  Kevin W. BREW ,  Carl RADENS

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/823412 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78687 ,  H01L29/78696

Abstract: Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

公开(公告)号：US20210406181A1

公开(公告)日：2021-12-30

申请号：US17472764

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ahmet Serkan OZCAN ,  Tomasz KORNUTA ,  Carl RADENS ,  Nicolas ANTOINE

IPC: G06F12/0817 ,  G11C11/4076 ,  G06N3/063 ,  G06F12/02 ,  G06F16/33 ,  G11C11/4093

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

公开(公告)号：US20210357138A1

公开(公告)日：2021-11-18

申请号：US15929618

申请日：2020-05-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashish RANJAN ,  Arvind KUMAR ,  Carl RADENS

IPC: G06F3/06 ,  G06N3/04

Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.

公开(公告)号：US20160190312A1

公开(公告)日：2016-06-30

申请号：US14588337

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. ZHANG ,  Carl RADENS ,  Lawrence A. CLEVENGER ,  Yiheng XU

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/28 ,  H01L29/267 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/7827 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66666

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

Abstract translation: 公开了垂直GAA FET结构，其中载流纳米线基本上垂直于硅衬底的表面取向。 垂直GAA FET旨在满足7 nm技术生成的设计和性能标准。 在一些实施例中，可以经由衬底的背面制造垂直取向的GAA FET的漏极和栅极端子的电接触。 公开了各种n型和p型晶体管设计具有不同接触构造的实例。 在一个示例中，背面栅极触点延伸穿过相邻器件之间的隔离区域。 其他实施例具有用于电路设计灵活性的双栅极触点。 可以使用不同的接触配置来调整金属图案密度。