公开(公告)号：US20150187897A1

公开(公告)日：2015-07-02

申请号：US14657723

申请日：2015-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/423 ,  H01L29/49

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠，顶部上的底部，顶部和牺牲帽层; 栅极间隔物，源极和漏极区域，去除牺牲覆盖层之后在栅极堆叠的顶部和侧壁上的氮化物封装，氮化物封装上的有机平坦化层，对源极和漏极区域进行的硅化， 去除氮化物封装后的底部部分，有机平面化层和栅极叠层的顶部。

公开(公告)号：US09299795B2

公开(公告)日：2016-03-29

申请号：US14657723

申请日：2015-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠，顶部上的底部，顶部和牺牲帽层; 栅极间隔物，源极和漏极区域，去除牺牲覆盖层之后在栅极堆叠的顶部和侧壁上的氮化物封装，氮化物封装上的有机平坦化层，对源极和漏极区域进行的硅化， 去除氮化物封装后的底部部分，有机平面化层和栅极叠层的顶部。

公开(公告)号：US09041076B2

公开(公告)日：2015-05-26

申请号：US13757809

申请日：2013-02-03

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠：顶部上的底部，顶部和牺牲帽层; 门间隔; 源和漏区; 在除去牺牲帽层之后，在栅极堆叠的顶部和侧壁上的氮化物封装; 在氮化物封装之上的有机平面化层，平坦化封装; 并且在除去氮化物封装，有机平坦化层和栅极堆叠的顶部之后在源极和漏极区域和底部部分上进行硅化。