公开(公告)号：US20160099332A1

公开(公告)日：2016-04-07

申请号：US14968471

申请日：2015-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J. Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

公开(公告)号：US20130314981A1

公开(公告)日：2013-11-28

申请号：US13957937

申请日：2013-08-02

Applicant: International Business Machines Corporation

Inventor： John K. De Brosse ,  William J. Gallagher ,  Yu Lu

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  Y10S977/933

Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.

Abstract translation: 在一个实施例中，本发明是磁移位寄存器存储器件。 存储单元的一个实施例包括包括多个磁畴的磁柱，耦合到磁柱的读取器，用于从磁畴读取数据，用于存储从磁畴读取的数据的临时存储器和耦合到 磁柱，用于将临时存储器中的数据写入磁畴。

公开(公告)号：US09230624B2

公开(公告)日：2016-01-05

申请号：US14059985

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： John K. De Brosse ,  William J. Gallagher ,  Yu Lu

IPC: G11C19/00 ,  G11C11/16 ,  G11C11/14 ,  G11C19/08

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  Y10S977/933

Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.

公开(公告)号：US20150187897A1

公开(公告)日：2015-07-02

申请号：US14657723

申请日：2015-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/423 ,  H01L29/49

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠，顶部上的底部，顶部和牺牲帽层; 栅极间隔物，源极和漏极区域，去除牺牲覆盖层之后在栅极堆叠的顶部和侧壁上的氮化物封装，氮化物封装上的有机平坦化层，对源极和漏极区域进行的硅化， 去除氮化物封装后的底部部分，有机平面化层和栅极叠层的顶部。

公开(公告)号：US20140332862A1

公开(公告)日：2014-11-13

申请号：US13968101

申请日：2013-08-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.

Abstract translation: 堆叠晶体管器件包括形成在衬底上的下沟道层; 一对垂直对齐的源极区，形成在所述下部沟道层上，其中所述一对源极区被绝缘体隔开; 形成在下通道层上的一对垂直排列的漏极区，其中一对漏区由绝缘体分隔开; 形成在下栅极电介质层上的一对垂直排列的栅极区; 以及形成在源极区域，漏极区域和栅极区域上的上部沟道层。

公开(公告)号：US20140247639A1

公开(公告)日：2014-09-04

申请号：US14059985

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： JOHN K. DE BROSSE ,  William J. Gallagher ,  Yu Lu

IPC: G11C19/08

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  Y10S977/933

Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.

Abstract translation: 在一个实施例中，本发明是磁移位寄存器存储器件。 存储单元的一个实施例包括包括多个磁畴的磁柱，耦合到磁柱的读取器，用于从磁畴读取数据，用于存储从磁畴读取的数据的临时存储器和耦合到 磁柱，用于将临时存储器中的数据写入磁畴。

公开(公告)号：US09299795B2

公开(公告)日：2016-03-29

申请号：US14657723

申请日：2015-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠，顶部上的底部，顶部和牺牲帽层; 栅极间隔物，源极和漏极区域，去除牺牲覆盖层之后在栅极堆叠的顶部和侧壁上的氮化物封装，氮化物封装上的有机平坦化层，对源极和漏极区域进行的硅化， 去除氮化物封装后的底部部分，有机平面化层和栅极叠层的顶部。

公开(公告)号：US09041076B2

公开(公告)日：2015-05-26

申请号：US13757809

申请日：2013-02-03

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠：顶部上的底部，顶部和牺牲帽层; 门间隔; 源和漏区; 在除去牺牲帽层之后，在栅极堆叠的顶部和侧壁上的氮化物封装; 在氮化物封装之上的有机平面化层，平坦化封装; 并且在除去氮化物封装，有机平坦化层和栅极堆叠的顶部之后在源极和漏极区域和底部部分上进行硅化。

公开(公告)号：US20140332860A1

公开(公告)日：2014-11-13

申请号：US13890849

申请日：2013-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions.

Abstract translation: 用于形成堆叠晶体管的方法和系统。 这种方法包括在基底上形成下通道层; 在所述下通道层上形成一对垂直对准的栅极区; 在下通道材料上形成一对垂直排列的源极区域和一对垂直排列的漏极区域，每对漏极区域由绝缘体隔开; 在源极区域，漏极区域和栅极区域上形成上部沟道材料; 并提供对源极，漏极和栅极区域的电接入。

公开(公告)号：US09853116B2

公开(公告)日：2017-12-26

申请号：US14968471

申请日：2015-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J. Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.