公开(公告)号：US10892193B2

公开(公告)日：2021-01-12

申请号：US16585798

申请日：2019-09-27

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Veeraraghavan S. Baskar ,  Jay W. Strane ,  Ekmini Anuja De Silva

IPC: H01L21/8238 ,  H01L21/311 ,  H01L27/092 ,  H01L21/3105 ,  H01L29/66

Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

公开(公告)号：US10770361B2

公开(公告)日：2020-09-08

申请号：US16787762

申请日：2020-02-11

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Veeraraghavan S. Baskar ,  Jay W. Strane ,  Ekmini Anuja De Silva

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/092

Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

公开(公告)号：US09941134B2

公开(公告)日：2018-04-10

申请号：US15583638

申请日：2017-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US20170236717A1

公开(公告)日：2017-08-17

申请号：US15583638

申请日：2017-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L21/3065 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US11189532B2

公开(公告)日：2021-11-30

申请号：US16714766

申请日：2019-12-15

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Jay W. Strane ,  Eric Miller ,  Fee Li Lie ,  Richard A. Conti

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/027 ,  H01L29/10 ,  H01L21/311 ,  H01L29/786

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

公开(公告)号：US11043429B2

公开(公告)日：2021-06-22

申请号：US16741823

申请日：2020-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Jay W. Strane

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.

公开(公告)号：US10535550B2

公开(公告)日：2020-01-14

申请号：US15688154

申请日：2017-08-28

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Richard A. Conti ,  Dechao Guo ,  Devendra K. Sadana ,  Jay W. Strane

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

公开(公告)号：US09666474B2

公开(公告)日：2017-05-30

申请号：US14928817

申请日：2015-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US20170125286A1

公开(公告)日：2017-05-04

申请号：US14928817

申请日：2015-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US10672668B2

公开(公告)日：2020-06-02

申请号：US15993419

申请日：2018-05-30

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Jay W. Strane ,  Eric Miller ,  Fee Li Lie ,  Richard A. Conti

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/10

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.