公开(公告)号：US20200226040A1

公开(公告)日：2020-07-16

申请号：US16828380

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Stephen Glancy ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain

IPC: G06F11/16 ,  G11C29/42 ,  G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C29/52

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

公开(公告)号：US10671497B2

公开(公告)日：2020-06-02

申请号：US15875136

申请日：2018-01-19

Applicant: International Business Machines Corporation

Inventor： Stephen Glancy ,  Kyu-Hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain

IPC: G06F11/16 ,  G11C29/42 ,  G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C29/12

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

公开(公告)号：US20190018712A1

公开(公告)日：2019-01-17

申请号：US15650204

申请日：2017-07-14

Applicant: International Business Machines Corporation

Inventor： Briana E. Foxworth ,  Saravanan Sethuraman ,  Kevin M. Mcilvain ,  Lucas W. Mulkey ,  Adam J. McPadden

IPC: G06F9/50 ,  G05D23/19 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G05D23/19 ,  G06F1/3234 ,  G06F1/3275 ,  G06F9/5016

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

公开(公告)号：US09904611B1

公开(公告)日：2018-02-27

申请号：US15363163

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kyu-Hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain ,  Saravanan Sethuraman

IPC: G11C7/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F2201/805

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

公开(公告)号：US11593196B2

公开(公告)日：2023-02-28

申请号：US17539813

申请日：2021-12-01

Applicant: International Business Machines Corporation

Inventor： Kevin M. Mcilvain ,  Warren E. Maule ,  Stephen Glancy ,  Kyu-hyoun Kim ,  Edgar R. Cordero

IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16

Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

公开(公告)号：US10585754B2

公开(公告)日：2020-03-10

申请号：US15678004

申请日：2017-08-15

Applicant: International Business Machines Corporation

Inventor： Briana E. Foxworth ,  Saravanan Sethuraman ,  Lucas W. Mulkey ,  Adam J. McPadden ,  Kevin M. Mcilvain

IPC: G06F11/00 ,  G06F11/14 ,  G06F13/40 ,  G11C5/14 ,  G06F3/06 ,  G11C7/20 ,  G11C14/00 ,  G06F12/02 ,  G06F21/79 ,  G06F21/44 ,  G06F11/20

Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

公开(公告)号：US20190310896A1

公开(公告)日：2019-10-10

申请号：US16423293

申请日：2019-05-28

Applicant: International Business Machines Corporation

Inventor： Briana E. Foxworth ,  Saravanan Sethuraman ,  Kevin M. Mcilvain ,  Lucas W. Mulkey ,  Adam J. McPadden

IPC: G06F9/50 ,  G05D23/19 ,  G06F1/3234

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

公开(公告)号：US20190033952A1

公开(公告)日：2019-01-31

申请号：US15684332

申请日：2017-08-23

Applicant: International Business Machines Corporation

Inventor： Kevin M. Mcilvain ,  Saravanan Sethuraman ,  Warren E. Maule ,  Kyu-hyoun Kim

IPC: G06F1/32 ,  G06F9/44

Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

公开(公告)号：US20190018713A1

公开(公告)日：2019-01-17

申请号：US15691230

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Briana E. Foxworth ,  Saravanan Sethuraman ,  Kevin M. Mcilvain ,  Lucas W. Mulkey ,  Adam J. McPadden

IPC: G06F9/50 ,  G06F1/32 ,  G05D23/19

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

公开(公告)号：US10042726B2

公开(公告)日：2018-08-07

申请号：US15841798

申请日：2017-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kyu-Hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain ,  Saravanan Sethuraman

IPC: G11C7/10 ,  G06F11/20

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.