公开(公告)号：US11011415B2

公开(公告)日：2021-05-18

申请号：US16858484

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US10796949B2

公开(公告)日：2020-10-06

申请号：US16165251

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US20200258770A1

公开(公告)日：2020-08-13

申请号：US16858484

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L21/768 ,  H01L23/522

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US20240203816A1

公开(公告)日：2024-06-20

申请号：US18067207

申请日：2022-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kisik Choi ,  Nicholas Alexander POLOMOFF ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Terence Hook ,  Matthew Angyal ,  FEE LI LIE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L23/3735 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80447 ,  H01L2924/0504 ,  H01L2924/0544

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer. A back-end-of-line (BEOL) layer includes a thermal transfer structure in contact with the FEOL layer. A carrier wafer is bonded to the BEOL layer and includes a thermal dissipation structure in contact with the thermal transfer structure.

公开(公告)号：US20200126842A1

公开(公告)日：2020-04-23

申请号：US16165251

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L21/768 ,  H01L23/522

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.