公开(公告)号：US12176289B2

公开(公告)日：2024-12-24

申请号：US17656368

申请日：2022-03-24

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Terence Hook

IPC: H01L23/528 ,  H01L27/092

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

公开(公告)号：US20240379657A1

公开(公告)日：2024-11-14

申请号：US18195677

申请日：2023-05-10

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Junli Wang ,  Chen Zhang ,  Anthony I. Chou

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/861

Abstract: A semiconductor structure is provided including stacked first and second devices wherein at least one of the stacked devices includes a lateral diode. The lateral diode includes a p-doped region as an anode, an n-doped region as a cathode and a semiconductor channel material region sandwiched between the anode and the cathode.

公开(公告)号：US20230062945A1

公开(公告)日：2023-03-02

申请号：US17411113

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Ryan Michael Kruse ,  Leon Sigal ,  Richard Edward Serton ,  Matthew Stephen Angyal ,  Terence Hook ,  Richard Andre Wachnik

IPC: G06F30/394 ,  H01L27/02

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

公开(公告)号：US20250006736A1

公开(公告)日：2025-01-02

申请号：US18214682

申请日：2023-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Biswanath Senapati ,  Shahrukh Khan ,  Utkarsh Bajpai ,  Terence Hook ,  Chen Zhang ,  Junli Wang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

公开(公告)号：US20250006664A1

公开(公告)日：2025-01-02

申请号：US18217008

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  FEE LI LIE ,  Ruilong Xie ,  Brent A. Anderson ,  Terence Hook ,  LEI ZHUANG ,  Kisik Choi

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528 ,  H01L23/60

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

公开(公告)号：US20240363617A1

公开(公告)日：2024-10-31

申请号：US18306487

申请日：2023-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence Hook ,  Brent A. Anderson ,  Ruilong Xie ,  Anthony I. Chou ,  John Christopher Arnold ,  Nicholas Alexander POLOMOFF

IPC: H01L27/02 ,  H01L21/84 ,  H02H9/04

CPC classification number: H01L27/0255 ,  H01L21/84 ,  H01L27/0292 ,  H02H9/046

Abstract: An ESD protection device is disclosed that uses a BSPDN to provide potential(s) to the ESD protection device. The utilization of the BSPDN reduces resistance drops induced during high current ESD events, which results in robust ESD protection. The utilization of the BSPDN also reduces the footprint area of the ESD protection circuit relative to known ESD protection devices that utilize respective frontside contacts to VDD, VSS, and I/O. Further, the disclosed ESD protection circuit may utilize the same or similar structures as that are used by microdevices (e.g., transistors, or the like) within the semiconductor IC device, which may decrease fabrication complexities thereof.

公开(公告)号：US20230411241A1

公开(公告)日：2023-12-21

申请号：US17841202

申请日：2022-06-15

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Brent A. Anderson ,  Anthony I. Chou

IPC: H01L23/427 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L23/427 ,  H01L27/1203 ,  H01L23/5226

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs

公开(公告)号：US20230317802A1

公开(公告)日：2023-10-05

申请号：US17657006

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Brent A Anderson ,  Terence Hook ,  Indira Seshadri ,  Albert M. Young ,  Stuart Sieg ,  Su Chen Fan ,  Shogo Mochizuki

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41725 ,  H01L29/401

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

公开(公告)号：US10128347B2

公开(公告)日：2018-11-13

申请号：US15398225

申请日：2017-01-04

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20180190782A1

公开(公告)日：2018-07-05

申请号：US15398225

申请日：2017-01-04

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.