公开(公告)号：US20250006664A1

公开(公告)日：2025-01-02

申请号：US18217008

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  FEE LI LIE ,  Ruilong Xie ,  Brent A. Anderson ,  Terence Hook ,  LEI ZHUANG ,  Kisik Choi

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528 ,  H01L23/60

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

公开(公告)号：US20240363617A1

公开(公告)日：2024-10-31

申请号：US18306487

申请日：2023-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence Hook ,  Brent A. Anderson ,  Ruilong Xie ,  Anthony I. Chou ,  John Christopher Arnold ,  Nicholas Alexander POLOMOFF

IPC: H01L27/02 ,  H01L21/84 ,  H02H9/04

CPC classification number: H01L27/0255 ,  H01L21/84 ,  H01L27/0292 ,  H02H9/046

Abstract: An ESD protection device is disclosed that uses a BSPDN to provide potential(s) to the ESD protection device. The utilization of the BSPDN reduces resistance drops induced during high current ESD events, which results in robust ESD protection. The utilization of the BSPDN also reduces the footprint area of the ESD protection circuit relative to known ESD protection devices that utilize respective frontside contacts to VDD, VSS, and I/O. Further, the disclosed ESD protection circuit may utilize the same or similar structures as that are used by microdevices (e.g., transistors, or the like) within the semiconductor IC device, which may decrease fabrication complexities thereof.

公开(公告)号：US20250006663A1

公开(公告)日：2025-01-02

申请号：US18216923

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Terence Hook ,  Matthew Stephen Angyal ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  FEE LI LIE ,  Ruilong Xie ,  LEI ZHUANG

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

公开(公告)号：US20250006629A1

公开(公告)日：2025-01-02

申请号：US18216978

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Terence Hook ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  FEE LI LIE ,  Ruilong Xie ,  LEI ZHUANG ,  Kisik Choi

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/60

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

公开(公告)号：US20250006590A1

公开(公告)日：2025-01-02

申请号：US18216887

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Matthew Stephen Angyal ,  Ruilong Xie ,  FEE LI LIE ,  Kisik Choi ,  Terence Hook ,  LEI ZHUANG

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/60 ,  H01L25/065 ,  H01L29/06

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

公开(公告)号：US20240203816A1

公开(公告)日：2024-06-20

申请号：US18067207

申请日：2022-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kisik Choi ,  Nicholas Alexander POLOMOFF ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Terence Hook ,  Matthew Angyal ,  FEE LI LIE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L23/3735 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80447 ,  H01L2924/0504 ,  H01L2924/0544

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer. A back-end-of-line (BEOL) layer includes a thermal transfer structure in contact with the FEOL layer. A carrier wafer is bonded to the BEOL layer and includes a thermal dissipation structure in contact with the thermal transfer structure.

公开(公告)号：US20250006681A1

公开(公告)日：2025-01-02

申请号：US18216404

申请日：2023-06-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Katsuyuki Sakuma ,  Akihiro Horibe ,  Takahito Watanabe ,  John Lucas Darling ,  Promod Roy Chowdhury ,  Keodara Seifert

IPC: H01L23/00 ,  H01L23/498

Abstract: A unified crackstop structure is described incorporating at least two semiconductor builds, each having a crackstop structure on its periphery and a metal wall or line extending from one crackstop structure to the other.

公开(公告)号：US20240170532A1

公开(公告)日：2024-05-23

申请号：US18056731

申请日：2022-11-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Koichi Motoyama ,  Nicholas Alexander POLOMOFF ,  Leon Sigal

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) comprising a first source/drain (S/D), a second FET comprising a second S/D squarely above the first S/D, and a shared S/D contact. The shared S/D may include a recessed portion between the first S/D and the second S/D, a side portion above the recessed portion, and a top portion above the second S/D. The side portion may contact a lateral side of the second S/D.

公开(公告)号：US20250004208A1

公开(公告)日：2025-01-02

申请号：US18342127

申请日：2023-06-27

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander POLOMOFF ,  Nicholas Latham ,  Junwon Han ,  Kishan Jayanand ,  Mary McGahay ,  Sathyanarayanan Raghavan ,  Aakrati Jain

IPC: G02B6/36

Abstract: A lid for a photonic device includes a resilient frame configured to bridge transversely over one or more optical fibers in a region of the photonic device. The resilient frame includes a span that defines a span direction, the resilient frame further includes end portions that are disposed transversely to the span to form an internal region of the frame. A compliant solid base material is formed within the internal region of the frame and attached to the frame along the span. The resilient frame is configured to transversely span over one or more optical fibers and preload the one or more optical fibers with the compliant solid base material when secured to the photonic device.

公开(公告)号：US20240194691A1

公开(公告)日：2024-06-13

申请号：US18064954

申请日：2022-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Tao Li ,  Nicholas Alexander POLOMOFF ,  Chih-Chao Yang

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1266 ,  H01L27/1251

Abstract: A first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. Forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.