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    INITIALIZING I/O DEVICES
    2.
    发明申请
    INITIALIZING I/O DEVICES 有权
    初始化I / O设备

    公开(公告)号：US20160098363A1

    公开(公告)日：2016-04-07

    申请号：US14862221

    申请日：2015-09-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert HAGSPIEL ,  Sascha JUNGHANS ,  Matthias KLEIN ,  Joerg WALTER

    IPC: G06F13/10 ,  G06F13/40 ,  G06F13/20

    CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4068

    Abstract: A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.

    Abstract translation: 提供了一种数据处理系统，其包括通过总线控制器通信地耦合到输入/输出总线的处理器套件，以及通信地耦合到处理器嵌套的服务接口控制器。 该系统包括用于存储用于总线控制器的命令和相关联的命令数据和所得到的状态数据的存储器，该存储器通信地耦合到处理器嵌套和总线控制器。 服务接口控制器被配置为响应于接收到的服务命令来读取和写入存储器，以执行存储器中指定的命令，以检索命令的结果，并将结果存储在存储器中。

    EFFICIENT SOFTWARE CLOSING OF HARDWARE-GENERATED ENCODING CONTEXT
    3.
    发明申请
    EFFICIENT SOFTWARE CLOSING OF HARDWARE-GENERATED ENCODING CONTEXT 审中-公开

    公开(公告)号：US20190312588A1

    公开(公告)日：2019-10-10

    申请号：US16358764

    申请日：2019-03-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony T. SOFIA ,  Jonathan D. BRADBURY ,  Matthias KLEIN ,  Bruce GIAMEI

    IPC: H03M7/30 ,  H03M7/40

    Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

    DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTION
    4.
    发明申请
    DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTION 审中-公开

    公开(公告)号：US20180024812A1

    公开(公告)日：2018-01-25

    申请号：US15722429

    申请日：2017-10-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sascha JUNGHANS ,  Matthias KLEIN ,  Thomas SCHLIPF

    IPC: G06F7/544

    Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

    DATA PROCESSING APPARATUS AND METHOD
    6.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD 审中-公开
    数据处理装置和方法

    公开(公告)号：US20160055107A1

    公开(公告)日：2016-02-25

    申请号：US14827636

    申请日：2015-08-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ekaterina M. AMBROLADZE ,  Norbert HAGSPIEL ,  Sascha JUNGHANS ,  Matthias KLEIN ,  Joerg WALTER

    IPC: G06F13/28 ,  G06F12/08

    CPC classification number: G06F13/28 ,  G06F12/084 ,  G06F12/0862 ,  G06F2212/6028

    Abstract: A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.

    Abstract translation: 提供了一种数据处理装置，其包括：多个处理器核; 共享处理器高速缓存，共享处理器高速缓存连接到每个处理器核心和主存储器; 总线控制器，总线控制器连接到共享处理器高速缓存，并且响应于接收到处理器核心之一发送的描述符，执行由描述符指示的请求数据从共享处理器高速缓存传送到输入/输出 （I / O）设备; 总线单元，总线单元连接到总线控制器并将数据传送到I / O设备; 其中所述共享处理器高速缓存包括用于响应于从所述处理器核之一接收描述符而通过执行直接存储器访问来从所述共享处理器高速缓存或主存储器预取所请求的数据的装置。

    DATA TRANSFER USING A DESCRIPTOR
    9.
    发明申请
    DATA TRANSFER USING A DESCRIPTOR 审中-公开

    公开(公告)号：US20190332559A1

    公开(公告)日：2019-10-31

    申请号：US16451650

    申请日：2019-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert HAGSPIEL ,  Sascha JUNGHANS ,  Matthias KLEIN ,  Joerg WALTER

    IPC: G06F13/28 ,  G06F12/084

    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

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