Abstract:
One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
Abstract:
Aspects include a method for generating a signal in response to an event. The method includes receiving, from a clock signal generator, a clock signal, wherein the clock signal has a fixed clock period. The method further includes receiving an indication of a pulse and, responsive to receiving the indication of the pulse, generating an output comprising a high voltage having a starting time and an ending time. The starting time is a first time when the indication of the asynchronous event is received, and the ending time is a second time at one fixed clocked period from the starting time.
Abstract:
An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.
Abstract:
An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.
Abstract:
One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
Abstract:
Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.
Abstract:
Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
Abstract:
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.
Abstract:
One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
Abstract:
One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.