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公开(公告)号：US20180211377A1
公开(公告)日：2018-07-26
申请号：US15414569
申请日：2017-01-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Andrea Bahgat Shehata , Peilin Song , Franco Stellari , Alan J. Weger
CPC classification number: G06T7/0004 , G01N21/9501 , G01N21/95607 , G01N2201/13 , G06K9/6201 , G06K9/6267 , G06T11/20 , G06T2207/30148 , H01L22/30 , H01L23/57 , H01L23/573
Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.
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公开(公告)号：US09678152B2
公开(公告)日：2017-06-13
申请号：US15138737
申请日：2016-04-26
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G06F11/00 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
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公开(公告)号：US20170097389A1
公开(公告)日：2017-04-06
申请号：US15138737
申请日：2016-04-26
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
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公开(公告)号：US10552278B2
公开(公告)日：2020-02-04
申请号：US16035032
申请日：2018-07-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/00 , G06F11/22 , G06F11/24 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.
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公开(公告)号：US10147175B2
公开(公告)日：2018-12-04
申请号：US15414569
申请日：2017-01-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Andrea Bahgat Shehata , Peilin Song , Franco Stellari , Alan J. Weger
Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160003902A1
公开(公告)日：2016-01-07
申请号：US14722377
申请日：2015-05-27
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
Abstract translation: 公开了扫描链锁存电路，操作扫描链中的锁存电路的方法，以及其上存储有限定用于在半导体管芯上实例化的扫描链锁存电路的数据结构的计算机可读介质。 在一个实施例中，扫描链锁存电路包括用于保存一个数据值的第一锁存器，用于保存另一个数据值的第二锁存器和多路复用器。 一个数据值被应用于多路复用器的第一数据输入端，并且另一个数据值被应用于多路复用器的第二数据输入端。 交替时钟信号被施加到多路复用器的选择输入端以控制多路复用器的输出，其中多路复用器的输出在保持在两个锁存器中的两个数据值之间以定义的频率切换。
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公开(公告)号：US10571520B2
公开(公告)日：2020-02-25
申请号：US15590617
申请日：2017-05-09
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G01R31/28 , G01R31/3177 , G01R31/3185 , G01R31/317
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
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公开(公告)号：US20180322025A1
公开(公告)日：2018-11-08
申请号：US16035032
申请日：2018-07-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
CPC classification number: G06F11/2236 , G06F11/008 , G06F11/2273 , G06F11/24 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.
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公开(公告)号：US09930325B2
公开(公告)日：2018-03-27
申请号：US14939788
申请日：2015-11-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Herschel A Ainspan , Seongwon Kim , Franco Stellari , Alan J. Weger
CPC classification number: H04N17/002 , G01J1/44 , G01J11/00 , G01J2001/4238 , G01R31/26 , H03K19/094 , H03K19/14
Abstract: Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.
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公开(公告)号：US20170329685A1
公开(公告)日：2017-11-16
申请号：US15156136
申请日：2016-05-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/22 , G06F11/263
CPC classification number: G06F11/2236 , G06F11/008 , G06F11/24
Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.
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