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    Charge recycling between power domains of integrated circuits
    1.
    发明授权
    Charge recycling between power domains of integrated circuits 有权
    集成电路电源域之间的充电回收

    公开(公告)号：US08984314B2

    公开(公告)日：2015-03-17

    申请号：US14083887

    申请日：2013-11-19

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Joachim Keinert ,  Antje Mueller ,  Tim Niggemeier

    IPC: G06F1/32 ,  G06F1/00

    CPC classification number: G06F1/3234 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/76

    Abstract: A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally be lost due to leakage.

    Abstract translation: 提供了一种用于从放电的动力区域有效地再循环电荷的机构。 通常耦合到电压源的放电电源域的一侧与电压源断开。 通常耦合到电压源的预充电功率域的一侧当前与电压源断开。 通常耦合到电压源的放电功率域的一侧连接到通常耦合到电压源的预充电功率域的一侧。 通常耦合到地面的放电电源域的一侧与地面断开。 通常耦合到地的放电电源域的一侧连接到电压源，从而由通常由于泄漏而通常丢失的放电电源域的电荷预充电预充电功率域。

    Pipelining out-of-order instructions
    2.
    发明授权
    Pipelining out-of-order instructions 有权

    公开(公告)号：US09733945B2

    公开(公告)日：2017-08-15

    申请号：US15058902

    申请日：2016-03-02

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Tim Niggemeier

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3836 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3869 ,  G06F9/3873

    Abstract: Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for short instructions of a short latency type and long instructions of a long latency type, an issue queue containing at least two short instructions of a short latency type, which are to be chained to match a latency of a long instruction of a long latency type, a register file, at least one execution pipeline for instructions of a short latency type and at least one execution pipeline for instructions of a long latency type; wherein results of the at least one execution pipeline for instructions of the short latency type are written to the register file, preserved in an auxiliary buffer, or forwarded to inputs of said execution pipelines. Data of the auxiliary buffer are written to the register file.

    Charge Recycling Between Power Domains of Integrated Circuits
    3.
    发明申请
    Charge Recycling Between Power Domains of Integrated Circuits 有权
    集成电路电源域之间的充电回收

    公开(公告)号：US20140082386A1

    公开(公告)日：2014-03-20

    申请号：US14083887

    申请日：2013-11-19

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Joachim Keinert ,  Antje Mueller ,  Tim Niggemeier

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/76

    Abstract: A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally be lost due to leakage.

    Abstract translation: 提供了一种用于从放电的动力区域有效地再循环电荷的机构。 通常耦合到电压源的放电电源域的一侧与电压源断开。 通常耦合到电压源的预充电功率域的一侧当前与电压源断开。 通常耦合到电压源的放电功率域的一侧连接到通常耦合到电压源的预充电功率域的一侧。 通常耦合到地面的放电电源域的一侧与地面断开。 通常耦合到地的放电电源域的一侧连接到电压源，从而由通常由于泄漏而通常丢失的放电电源域的电荷预充电预充电功率域。

    Pipelining out-of-order instructions
    4.
    发明授权
    Pipelining out-of-order instructions 有权
    流通无序的指示

    公开(公告)号：US09395996B2

    公开(公告)日：2016-07-19

    申请号：US13927372

    申请日：2013-06-26

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Tim Niggemeier

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3836 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3869 ,  G06F9/3873

    Abstract: Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for short instructions of a short latency type and long instructions of a long latency type, an issue queue containing at least two short instructions of a short latency type, which are to be chained to match a latency of a long instruction of a long latency type, a register file, at least one execution pipeline for instructions of a short latency type and at least one execution pipeline for instructions of a long latency type; wherein results of the at least one execution pipeline for instructions of the short latency type are written to the register file, preserved in an auxiliary buffer, or forwarded to inputs of said execution pipelines. Data of the auxiliary buffer are written to the register file.

    Abstract translation: 系统，方法和计算机程序产品提供流水线无序指令。 实施例包括用于短延迟类型的短指令的指令预留站和长延迟类型的长指令，包含短延迟类型的至少两个短指令的发布队列，其被链接以匹配长时延的等待时间 长延迟类型的指令，寄存器文件，用于短等待时间类型的指令的至少一个执行流水线和用于长等待时间类型的指令的至少一个执行流水线; 其中用于所述短延迟类型的指令的所述至少一个执行流水线的结果被写入所述寄存器文件，保存在辅助缓冲器中，或者被转发到所述执行管线的输入。 辅助缓冲器的数据被写入寄存器文件。

    PIPELINING OUT-OF-ORDER INSTRUCTIONS
    5.
    发明申请
    PIPELINING OUT-OF-ORDER INSTRUCTIONS 有权

    公开(公告)号：US20160179551A1

    公开(公告)日：2016-06-23

    申请号：US15058902

    申请日：2016-03-02

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Tim Niggemeier

    IPC: G06F9/38

    CPC classification number: G06F9/3836 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3869 ,  G06F9/3873

    Abstract: Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for short instructions of a short latency type and long instructions of a long latency type, an issue queue containing at least two short instructions of a short latency type, which are to be chained to match a latency of a long instruction of a long latency type, a register file, at least one execution pipeline for instructions of a short latency type and at least one execution pipeline for instructions of a long latency type; wherein results of the at least one execution pipeline for instructions of the short latency type are written to the register file, preserved in an auxiliary buffer, or forwarded to inputs of said execution pipelines. Data of the auxiliary buffer are written to the register file.

    Three-dimensional permute unit for a single-instruction multiple-data processor
    8.
    发明授权
    Three-dimensional permute unit for a single-instruction multiple-data processor 有权
    用于单指令多数据处理器的三维置换单元

    公开(公告)号：US09268738B2

    公开(公告)日：2016-02-23

    申请号：US13775355

    申请日：2013-02-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Harry Barowski ,  Tim Niggemeier

    IPC: G06F15/00 ,  G06F7/00 ,  G06F15/80 ,  G06F9/30

    CPC classification number: G06F15/803 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30141 ,  G06F15/8053

    Abstract: A three-dimensional (3D) permute unit for a single-instruction-multiple-data stacked processor includes a first vector permute subunit and a second vector permute subunit. The first and second vector permute subunits are arranged in different layers of a 3D chip package. The vector permute subunits are each configured to process a portion of at least two input vectors. A first contact sub-field of the first vector permute subunit is configured to connect output ports of a first crossbar of the first vector permute subunit, holding an intermediate result of the first vector permute subunit, to a second contact sub-field of the second vector permute subunit. A first contact sub-field of the second vector permute subunit is configured to connect output ports of a first crossbar of the second vector permute subunit, holding an intermediate result of the second vector permute subunit, to a second contact sub-field of the first vector permute subunit.

    Abstract translation: 用于单指令多数据堆叠处理器的三维（3D）置换单元包括第一向量置换子单元和第二向量置换子单元。 第一和第二矢量置换子单元布置在3D芯片封装的不同层中。 向量置换子单元被配置为处理至少两个输入向量的一部分。 第一矢量置换子单元的第一接触子场被配置为将保持第一矢量置换子单元的中间结果的第一矢量置换子单元的第一交叉开关的输出端口连接到第二矢量置换子单元的第二接触子场， 载体置换亚基。 第二矢量置换子单元的第一接触子场被配置为将保持第二矢量置换子单元的中间结果的第二矢量置换子单元的第一交叉开关的输出端口连接到第一矢量置换子单元的第一接触子场， 载体置换亚基。

    Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor
    9.
    发明申请
    Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor 审中-公开
    单指令多数据处理器的三维许可单位

    公开(公告)号：US20130227249A1

    公开(公告)日：2013-08-29

    申请号：US13775355

    申请日：2013-02-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Harry Barowski ,  Tim Niggemeier

    IPC: G06F15/80

    CPC classification number: G06F15/803 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30141 ,  G06F15/8053

    Abstract: A three-dimensional (3D) permute unit for a single-instruction-multiple-data stacked processor includes a first vector permute subunit and a second vector permute subunit. The first and second vector permute subunits are arranged in different layers of a 3D chip package. The vector permute subunits are each configured to process a portion of at least two input vectors. A first contact sub-field of the first vector permute subunit is configured to connect output ports of a first crossbar of the first vector permute subunit, holding an intermediate result of the first vector permute subunit, to a second contact sub-field of the second vector permute subunit. A first contact sub-field of the second vector permute subunit is configured to connect output ports of a first crossbar of the second vector permute subunit, holding an intermediate result of the second vector permute subunit, to a second contact sub-field of the first vector permute subunit.

    Abstract translation: 用于单指令多数据堆叠处理器的三维（3D）置换单元包括第一向量置换子单元和第二向量置换子单元。 第一和第二矢量置换子单元布置在3D芯片封装的不同层中。 向量置换子单元被配置为处理至少两个输入向量的一部分。 第一矢量置换子单元的第一接触子场被配置为将保持第一矢量置换子单元的中间结果的第一矢量置换子单元的第一交叉开关的输出端口连接到第二矢量置换子单元的第二接触子场， 载体置换亚基。 第二矢量置换子单元的第一接触子场被配置为将保持第二矢量置换子单元的中间结果的第二矢量置换子单元的第一交叉开关的输出端口连接到第一矢量置换子单元的第一接触子场， 载体置换亚基。

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