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1.发明申请公开(公告)号：US20200005848A1
公开(公告)日：2020-01-02
申请号：US16021575
申请日：2018-06-28
发明人： Martin M. Frank , Jin-Ping Han , Dennis M. Newns , Paul M. Solomon , Xiao Sun
摘要： A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
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公开(公告)号：US20190221559A1
公开(公告)日：2019-07-18
申请号：US16360690
申请日：2019-03-21
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L27/06 , H01L27/1159 , H01L21/28 , H01L27/11507
CPC分类号： H01L27/0629 , H01L27/11507 , H01L27/1159 , H01L29/0649 , H01L29/40111 , H01L29/4966 , H01L29/516
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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3.发明授权公开(公告)号：US11094820B2
公开(公告)日：2021-08-17
申请号：US16846461
申请日：2020-04-13
IPC分类号： H01L29/78 , H01L27/1159 , H01L29/66 , H01L21/28
摘要： A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
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公开(公告)号：US10332874B2
公开(公告)日：2019-06-25
申请号：US15585876
申请日：2017-05-03
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L29/772 , H01L27/06 , H01L29/51 , H01L29/49 , H01L29/06
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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公开(公告)号：US10804261B2
公开(公告)日：2020-10-13
申请号：US16662284
申请日：2019-10-24
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L27/06 , H01L27/11507 , H01L27/1159 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/28
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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公开(公告)号：US10755759B2
公开(公告)日：2020-08-25
申请号：US16021575
申请日：2018-06-28
发明人： Martin M. Frank , Jin-Ping Han , Dennis M. Newns , Paul M. Solomon , Xiao Sun
摘要： A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
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7.发明授权公开(公告)号：US10680105B2
公开(公告)日：2020-06-09
申请号：US15464943
申请日：2017-03-21
IPC分类号： H01L27/11585 , H01L29/78 , H01L27/1159 , H01L29/66 , H01L21/28
摘要： A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
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8.发明申请公开(公告)号：US20180277683A1
公开(公告)日：2018-09-27
申请号：US15464943
申请日：2017-03-21
IPC分类号： H01L29/78 , H01L27/1159 , H01L29/66
摘要： A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
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9.发明申请公开(公告)号：US20200243688A1
公开(公告)日：2020-07-30
申请号：US16846461
申请日：2020-04-13
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66 , H01L27/1159
摘要： A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
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公开(公告)号：US20200058641A1
公开(公告)日：2020-02-20
申请号：US16662284
申请日：2019-10-24
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L27/06 , H01L29/51 , H01L29/49 , H01L29/06 , H01L27/1159 , H01L27/11507 , H01L21/28
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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