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公开(公告)号：US20220058474A1
公开(公告)日：2022-02-24
申请号：US17518629
申请日：2021-11-04
发明人： Siyuranga Koswatta , Yulong Li , Paul M. Solomon
摘要： Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.
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2.发明授权公开(公告)号：US10896979B2
公开(公告)日：2021-01-19
申请号：US15718099
申请日：2017-09-28
发明人： Effendi Leobandung , Yulong Li , Tak Ning , Paul Michael Solomon , Chun-Chen Yeh
IPC分类号： H01L29/788 , H01L29/423 , H01L29/10 , H01L29/08 , H01L29/06 , H01L21/265 , H01L21/306 , H01L21/762 , H01L29/66 , H01L21/28
摘要： A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.
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公开(公告)号：US10804261B2
公开(公告)日：2020-10-13
申请号：US16662284
申请日：2019-10-24
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L27/06 , H01L27/11507 , H01L27/1159 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/28
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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公开(公告)号：US20200152741A1
公开(公告)日：2020-05-14
申请号：US16747027
申请日：2020-01-20
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/80 , H01L29/66 , H01L29/205 , H01L29/49 , H01L29/68 , H01L29/06 , H01L29/423 , H01L27/24 , H01L29/788 , H01L27/108 , H01L21/28 , H01L29/165 , H01L29/78 , H01L29/51 , H01L27/1159 , H01L27/11521
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US10374041B2
公开(公告)日：2019-08-06
申请号：US15850098
申请日：2017-12-21
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L29/78 , H01L29/788
摘要： Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
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公开(公告)号：US20190198617A1
公开(公告)日：2019-06-27
申请号：US15850098
申请日：2017-12-21
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
CPC分类号： H01L29/1045 , H01L29/0646 , H01L29/1054 , H01L29/165 , H01L29/205 , H01L29/4983 , H01L29/66431 , H01L29/66659 , H01L29/66825 , H01L29/6684 , H01L29/66977 , H01L29/685 , H01L29/78391 , H01L29/788 , H01L29/802
摘要： Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
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7.发明申请公开(公告)号：US20190180174A1
公开(公告)日：2019-06-13
申请号：US15840322
申请日：2017-12-13
发明人： Siyuranga Koswatta , Yulong Li , Paul M. Solomon
摘要： Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example method includes setting a state of each single bit counter from a set of single bit counters in the crosspoint device, the states of the single bit counters representing the weight to be stored at the crosspoint device. The method further includes adjusting electrical conductance of a resistor device of the crosspoint device. The resistor device includes a set of resistive circuits, each resistive circuit associated with a respective single bit counter from the set of single bit counters, the electrical conductance adjusted by activating or deactivating each resistive circuit according to a state of the associated single bit counter.
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公开(公告)号：US10319439B1
公开(公告)日：2019-06-11
申请号：US15979759
申请日：2018-05-15
发明人： Yulong Li , Paul M. Solomon
摘要： A resistive processing unit includes a first analog memory element, a second analog memory element connected in series with the first analog memory element, and a control circuit coupled to the first analog memory element and the second analog memory element. The control circuit is configured to read a synaptic weight value of the resistive processing unit by collecting a differential current from the first analog memory element and the second analog memory element on at least one of a read column line and a read row line coupled to a terminal coupling the first analog memory element and the second analog memory element.
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公开(公告)号：US20190005382A1
公开(公告)日：2019-01-03
申请号：US15820114
申请日：2017-11-21
发明人： Yulong Li , Paul Solomon , Effendi Leobandung , Chun-Chen Yeh , Seyoung Kim
摘要： A CMOS-based resistive processing unit (RPU) and method for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.
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公开(公告)号：US12015056B2
公开(公告)日：2024-06-18
申请号：US18306359
申请日：2023-04-25
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L21/28 , H01L29/06 , H01L29/165 , H01L29/205 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/68 , H01L29/78 , H01L29/788 , H01L29/80 , H10B12/00 , H10B41/30 , H10B51/30 , H10B63/00
CPC分类号： H01L29/1045 , H01L29/0646 , H01L29/1054 , H01L29/165 , H01L29/205 , H01L29/40111 , H01L29/40114 , H01L29/42324 , H01L29/4983 , H01L29/516 , H01L29/66431 , H01L29/66659 , H01L29/66977 , H01L29/685 , H01L29/785 , H01L29/7881 , H01L29/802 , H10B12/30 , H10B41/30 , H10B51/30 , H10B63/00 , H01L29/66825 , H01L29/6684 , H01L29/78391 , H01L29/788
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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