公开(公告)号：US09966387B2

公开(公告)日：2018-05-08

申请号：US15343387

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

公开(公告)号：US09761610B2

公开(公告)日：2017-09-12

申请号：US15242992

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

公开(公告)号：US20170250073A1

公开(公告)日：2017-08-31

申请号：US15595503

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L21/02 ,  H01L21/20 ,  H01G4/005 ,  H01L21/322

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US09653534B2

公开(公告)日：2017-05-16

申请号：US14572974

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L29/66 ,  H01L49/02 ,  H01L27/108 ,  H01L23/26

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US20170053994A1

公开(公告)日：2017-02-23

申请号：US14830789

申请日：2015-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/0332 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Abstract translation: 在FinFET器件的沟道区域中引入应变的方法包括在衬底上形成翅片结构，鳍结构具有包括牺牲层的下部和包括应变半导体层的上部; 以及去除与FinFET器件的沟道区相对应的牺牲层的一部分，以便在沟道区中从衬底释放翅片结构的上部。

公开(公告)号：US09349658B1

公开(公告)日：2016-05-24

申请号：US14608625

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.

Abstract translation: 一个说明性实施例涉及在衬底中形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一氧化阻挡层，以便覆盖下部分的侧壁的一部分但不是全部 在绝缘材料的第一氧化阻挡层之上形成第二绝缘材料层，并进行热退火处理以将位于第一氧化阻挡层之上的翅片的下部的部分转化而不是全部 绝缘材料层形成位于翅片下方的氧化物鳍片隔离区域。

公开(公告)号：US09318489B2

公开(公告)日：2016-04-19

申请号：US14805529

申请日：2015-07-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

公开(公告)号：US20160086858A1

公开(公告)日：2016-03-24

申请号：US14495342

申请日：2014-09-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

公开(公告)号：US20150364603A1

公开(公告)日：2015-12-17

申请号：US14305543

申请日：2014-06-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US20150357470A1

公开(公告)日：2015-12-10

申请号：US14802110

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/76205 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided.

Abstract translation: 一种用于在半导体鳍片结构的沟道内引发应力的方法包括在衬底上形成半导体鳍片; 在半导体翅片上形成翅片硬掩模层，多个隔离区域和多个间隔物; 在半导体鳍片上形成栅极结构; 以及氧化半导体鳍片的多个外部区域以产生在半导体鳍片的沟道内引起压应力的氧化应激物。 还提供了通过氧化半导体鳍片的中心区域来在半导体鳍片的沟道内引起拉伸应力的方法。 还提供了与方法对应的结构。