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公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译： 用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。 在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。 在失控状态下，计数器不复位，并触发VCO的控制信号。 第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。 当第一个计数器远远超出第二个计数器时，触发控制信号。
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公开(公告)号：US5220581A
公开(公告)日：1993-06-15
申请号：US676638
申请日：1991-03-28
CPC分类号： H04L43/00 , H04L1/24 , H04L12/2602 , H04L7/0334 , H04L7/0337 , H04L43/0817 , H04L43/087 , H04L43/16
摘要： A digital data link performance monitor technique for communication systems and information and data processing systems is disclosed. The technique is based on the integration and analysis of a plurality of sorted data edge transitions of a serial data stream received over the digital data link. The number of data edge sorts to each of n time intervals definitive of the edge histogram is compared with a predetermined threshold level and a monitor signal is generated with each comparison. The combination of monitor signals is then analyzed to determine the amount of data timing jitter, and therefore the quality of the link. Corresponding methods and circuits are described.
摘要翻译： 公开了用于通信系统和信息和数据处理系统的数字数据链路性能监视技术。 该技术基于通过数字数据链路接收的串行数据流的多个排序数据边缘转换的集成和分析。 将边缘直方图的n个时间间隔确定的每一个的数据边缘排列次数与预定的阈值电平进行比较，并且通过每个比较生成监视信号。 然后分析监视信号的组合以确定数据定时抖动的量，并因此确定链路的质量。 描述相应的方法和电路。
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公开(公告)号：US5825226A
公开(公告)日：1998-10-20
申请号：US529850
申请日：1995-09-18
CPC分类号： H03L7/0895 , H03K5/133 , H03L7/0812
摘要： A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.
摘要翻译： 提供了用于最小化PLL中的静态相位误差的延迟均衡电路。 延迟均衡电路包括外部时钟信号可变延迟路径和用于产生具有与外部时钟信号可变延迟路径的延迟成比例的宽度的脉冲的元件。 延迟均衡电路还包括反馈回路中的延迟路径，以及用于与内部延迟路径的延迟成比例地产生第二脉冲的第二元件。 最后，该电路包含比较装置。 比较装置比较第一和第二脉冲。 比较装置与外部和内部路径延迟的差异成比例地输出差分信号。 该差分信号被反馈并用于控制外部路径延迟，使得外部延迟被驱动为基本上等于内部延迟，从而最小化PLL器件的静态相位误差。
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公开(公告)号：US5627456A
公开(公告)日：1997-05-06
申请号：US477208
申请日：1995-06-07
CPC分类号： G05F3/262 , Y10S323/907
摘要： An integrated current reference circuit provides a current output with a predetermined temperature coefficient, suitably zero, to provide constant current over temperature variations. The circuit is formed of only Field Effect Transistors (FETs), allowing the circuit to be implemented using conventional CMOS fabrication techniques. A current mirror provides a reference current in both branches of the circuit. The output of the current mirror is coupled to a circuit providing an imbalance in resistance between the two branches, and an offsetting imbalance in voltages between the two branches, resulting in a reference current that has a predetermined temperature coefficient. An output current is provided which is proportional to the reference current and thus has the same temperature coefficient as the reference current.
摘要翻译： 集成电流参考电路为电流输出提供预定的温度系数，适当地为零，以提供恒定电流超过温度变化。 该电路仅由场效应晶体管（FET）形成，允许使用常规CMOS制造技术实现电路。 电流镜在电路的两个分支中提供参考电流。 电流镜的输出耦合到提供两个分支之间的电阻不平衡的电路和两个分支之间的电压的偏移不平衡，导致具有预定温度系数的参考电流。 提供与参考电流成比例的输出电流，因此具有与参考电流相同的温度系数。
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公开(公告)号：US5212716A
公开(公告)日：1993-05-18
申请号：US650516
申请日：1991-02-05
CPC分类号： H04L7/0338 , H03L7/0814
摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.
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公开(公告)号：US5185768A
公开(公告)日：1993-02-09
申请号：US594242
申请日：1990-10-09
CPC分类号： H04L7/0338
摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.
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公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译： 描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。 定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部 时钟信号输入到半导体芯片一个周期。 描述和要求保护各种定时网络实施例。
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公开(公告)号：US5295155A
公开(公告)日：1994-03-15
申请号：US968716
申请日：1992-10-30
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
CPC分类号： H04L7/0338 , H04L25/062 , H04L25/066 , H04L7/0334
摘要： An adaptive regeneration system is provided for reconstructing a signal received in the form of a multi-level composite data and clock signal which has been degraded with respect to amplitude and timing. The system includes a local clock circuit for outputting a plurality of phase-delayed local clock signals, and a clock recovery circuit for receiving the received multi-level signal and the plurality of phase-delayed clock signals and extracting a phase-delayed local clock signal which most accurately represents the phase shift between the received multi-level signal and the local clock signal. A threshold level selection circuit receives the extracted phase-delayed local clock signal and the received multi-level signal and outputs in real time a data amplitude reading and a plurality of multi-level threshold levels corresponding to the amplitude levels of the received multi-level signal. A data regenerator receives the data amplitude reading, the plurality of multi-level threshold levels and the extracted phase-delayed signal and reconstructs and outputs the received multi-level signal essentially in its originally transmitted form.
摘要翻译： 提供了一种自适应再生系统，用于重建以多级复合数据形式接收的信号和相对于幅度和定时已经劣化的时钟信号。 该系统包括用于输出多个相位延迟的本地时钟信号的本地时钟电路，以及用于接收所接收的多电平信号和多个相位延迟的时钟信号的时钟恢复电路，并且提取相位延迟的本地时钟信号 其最准确地表示接收的多电平信号和本地时钟信号之间的相移。 阈值电平选择电路接收所提取的相位延迟的本地时钟信号和接收的多电平信号，并实时输出数据振幅读取和与所接收的多电平的幅度电平对应的多个多电平阈值电平 信号。 数据再生器接收数据幅度读取，多个多电平阈值电平和提取的相位延迟信号，并且以原始发送的形式重建并输出所接收的多电平信号。
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公开(公告)号：US5293405A
公开(公告)日：1994-03-08
申请号：US785488
申请日：1991-10-31
CPC分类号： H04L25/03885
摘要： An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output. Control logic is used to identify the slope of the equalizer gain function at which total signal degradation is minimized. The control signal, which corresponds to this identified slope, is applied to the equalizer in real time to maintain minimum total signal degradation at the equalizer output.
摘要翻译： 提供了一种自适应均衡和再生系统，用于精确地重构已经相对于振幅和瞬时频率退化的接收数据脉冲串。 该系统包括均衡器，其响应于控制信号以为接收信号提供可变增益函数并输出均衡信号，用于从均衡信号接收和提取定时信息的数字锁相逻辑，用于将定时信息与 用于以原始发送形式重建接收数据的均衡信号，以及用于向均衡器提供控制信号的控制电路。 控制信号调整均衡器增益函数的斜率，以便最小化均衡器输出端的幅度和瞬时频率衰减。 该系统包括一个检测和计算均衡器输出端总信号衰减的机制。 控制逻辑用于识别总信号劣化最小化的均衡器增益函数的斜率。 将对应于该识别的斜率的控制信号实时地施加到均衡器，以保持均衡器输出处的最小总信号劣化。
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10.发明授权Clock extraction and data regeneration logic for multiple speed data communications systems 失效用于多速数据通信系统的时钟提取和数据再生逻辑
公开(公告)号：US5371766A
公开(公告)日：1994-12-06
申请号：US979121
申请日：1992-11-20
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
CPC分类号： H04L7/0337 , H04L12/422
摘要： Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which connect stations in the LAN to other stations in the LAN via transmission media such as wire or fiber optic cable. The clock extraction and data regeneration logic is adapted to quickly recognize the speed at which the token ring is operating, thereby preventing a station on the ring from sending data onto the ring at a rate which does not match the operating frequency of the ring. The logic also performs, at multiple speeds of operation, clock extraction and data reconstruction of a signal received from another station in the ring.
摘要翻译： 为诸如局域网（LAN）的多速率数字数据通信系统提供时钟提取和数据再生逻辑。 逻辑是通过适配器实现的，这些适配器通过诸如有线或光纤电缆的传输介质将LAN中的站与LAN中的其他站连接。 时钟提取和数据再生逻辑适于快速识别令牌环操作的速度，从而防止环上的站以与环的工作频率不匹配的速率将数据发送到环上。 该逻辑还在多个操作速度下执行从环中的另一个站接收的信号的时钟提取和数据重建。
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