-
1.发明授权Apparatus for providing data to a plurality of graphics processors and method thereof 有权用于向多个图形处理器提供数据的装置及其方法公开(公告)号：US06633296B1
公开(公告)日：2003-10-14
申请号：US09579432
申请日：2000-05-26
申请人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
发明人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G09G5/363 , G09G2352/00 , G09G2360/06
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换
-
公开(公告)号：US06789154B1
公开(公告)日：2004-09-07
申请号：US09579203
申请日：2000-05-26
申请人： Brian Lee , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
发明人： Brian Lee , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
IPC分类号： G06F1314
CPC分类号： G06F13/404
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
-
公开(公告)号：US06670958B1
公开(公告)日：2003-12-30
申请号：US09579224
申请日：2000-05-26
申请人： Milivoje Aleksic , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
发明人： Milivoje Aleksic , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G09G5/363 , G09G2352/00
摘要： In a specific embodiment, a system for providing video includes a system bus, which in one embodiment is an Advanced Graphics Port (AGP) busy. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，用于提供视频的系统包括系统总线，其在一个实施例中是高级图形端口（AGP）忙。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
-
公开(公告)号：US06662257B1
公开(公告)日：2003-12-09
申请号：US09579202
申请日：2000-05-26
申请人： Gordon Caruk , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Milivoje Aleksic , Brian Lee
发明人： Gordon Caruk , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Milivoje Aleksic , Brian Lee
IPC分类号： G06F1314
CPC分类号： G06F13/404 , G06F3/14
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
-
5.发明授权Method of configuring, controlling, and accessing a bridge and apparatus therefor 有权配置，控制和访问其桥及其设备的方法公开(公告)号：US06728820B1
公开(公告)日：2004-04-27
申请号：US09579006
申请日：2000-05-26
申请人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
发明人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
IPC分类号： G06F1336
CPC分类号： G06F3/14
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
-
公开(公告)号：US6072507A
公开(公告)日：2000-06-06
申请号：US58949
申请日：1998-04-10
CPC分类号： G06F12/0207
摘要： A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whether the linear address is referencing a tiled surface, which is one of up to four portions of the memory. If so, the video graphics processor obtains parameters of the tiled surface. Having obtained the parameters, the video graphics processor determines a normalized linear address based on at least one of the parameters and the linear address. Having done this, the video graphics processor determines a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address and a modular function. In essence, the band pointer points to a normalized initial address of a band of a tiled surface, which includes a plurality of bands. Having obtained the band pointer, the video graphics processor then determines a linear band offset based on the band pointer and at least one of the parameters. Next, a tiled band offset is determined based on the linear band offset. Finally, the tiled address is determined based on the tiled band offset, the band pointer, and at least one of the parameters.
摘要翻译： 当视频图形处理器从中央处理单元接收到线性地址并确定线性地址是否参考平铺表面时，实现了将线性地址映射到平铺地址的方法和装置，其减少数据页面检索之间的等待时间， 这是记忆最多四部分之一。 如果是这样，则视频图形处理器获得平铺表面的参数。 在获得参数之后，视频图形处理器基于参数和线性地址中的至少一个来确定归一化的线性地址。 完成这一点后，视频图形处理器基于至少一个参数，归一化的线性地址和模块化功能来确定平铺表面的波段指针。 本质上，频带指针指向包括多个频带的平铺表面的频带的归一化初始地址。 在获得频带指针之后，视频图形处理器然后基于频带指针和至少一个参数来确定线性频带偏移。 接下来，基于线性带偏移确定平铺频带偏移。 最后，根据平铺频带偏移，频带指针和至少一个参数确定平铺地址。
-
公开(公告)号：US06658531B1
公开(公告)日：2003-12-02
申请号：US09614931
申请日：2000-07-12
申请人： Milivoje Aleksic , James Yee , Hon Ming Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Hon Ming Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译： 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。 根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。
-
公开(公告)号：US06173367B2
公开(公告)日：2001-01-09
申请号：US09314210
申请日：1999-05-19
申请人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译： 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。 根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。
-
9.发明授权公开(公告)号：US06486884B1
公开(公告)日：2002-11-26
申请号：US09314561
申请日：1999-05-19
IPC分类号： G06F1206
CPC分类号： H04N19/423
摘要： A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or column of data accessed by a burst frees up instruction bandwidth of a video controller. In particular, it is assured that each row and column of data associated with the data block has at least one sequential pair of data words associated with it. By assuring at least one sequential pair of data words, it is possible to issue a burst request for a minimum of two words of data with each row access, or column access of the video controller.
摘要翻译： 教导以数据块中的非线性方式存储与数据块相关联的顺序数据字的方法和装置，使得可以使用突发存取来访问与数据块相关联的任何行或列。 由突发访问的一行或一列数据释放视频控制器的指令带宽。 特别地，确保与数据块相关联的每一行和数据列具有与其相关联的至少一个连续数据字对。 通过确保至少一个顺序的数据字对，可以对视频控制器的每一行访问或列访问发出至少两个数据字的突发请求。
-
公开(公告)号：US08860721B2
公开(公告)日：2014-10-14
申请号：US11277641
申请日：2006-03-28
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.
摘要翻译： 用于处理像素深度信息的装置和方法通过对当前在像素流水线中的一个或多个像素执行后期Z处理以及进入像素流水线的一个或多个像素的早期Z处理来消除像素流水线中的数据的停止。 该装置和方法还包括确定当前在像素管线中的一个或多个像素的延迟Z处理是否已经完成。 该装置和方法还包括单独执行对进入像素流水线的后续像素的早期Z处理，以响应于确定当前在像素管线中的一个或多个像素的后期Z处理已经完成。 该方法和装置有助于早期和晚期Z数据的并发处理，以避免冲洗像素管道的部分。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.031 秒)