公开(公告)号：US06728820B1

公开(公告)日：2004-04-27

申请号：US09579006

申请日：2000-05-26

申请人： Lee Brian ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

发明人： Lee Brian ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

IPC分类号： G06F1336

CPC分类号： G06F3/14

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。

公开(公告)号：US06633296B1

公开(公告)日：2003-10-14

申请号：US09579432

申请日：2000-05-26

申请人： Indra Laksono ,  Milivoje Aleksic ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

发明人： Indra Laksono ,  Milivoje Aleksic ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

IPC分类号： G06F1516

CPC分类号： G06F3/14 ,  G09G5/363 ,  G09G2352/00 ,  G09G2360/06

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换

公开(公告)号：US06789154B1

公开(公告)日：2004-09-07

申请号：US09579203

申请日：2000-05-26

申请人： Brian Lee ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

发明人： Brian Lee ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

IPC分类号： G06F1314

CPC分类号： G06F13/404

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。

公开(公告)号：US06670958B1

公开(公告)日：2003-12-30

申请号：US09579224

申请日：2000-05-26

申请人： Milivoje Aleksic ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

发明人： Milivoje Aleksic ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

IPC分类号： G06F1516

CPC分类号： G06F3/14 ,  G09G5/363 ,  G09G2352/00

摘要： In a specific embodiment, a system for providing video includes a system bus, which in one embodiment is an Advanced Graphics Port (AGP) busy. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，用于提供视频的系统包括系统总线，其在一个实施例中是高级图形端口（AGP）忙。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。

公开(公告)号：US06662257B1

公开(公告)日：2003-12-09

申请号：US09579202

申请日：2000-05-26

申请人： Gordon Caruk ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Milivoje Aleksic ,  Brian Lee

发明人： Gordon Caruk ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Milivoje Aleksic ,  Brian Lee

IPC分类号： G06F1314

CPC分类号： G06F13/404 ,  G06F3/14

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。

公开(公告)号：US06184908B2

公开(公告)日：2001-02-06

申请号：US09067512

申请日：1998-04-27

申请人： Jason CK Chan ,  Milivoje Aleksic ,  Antonio Asaro ,  James Doyle ,  Indra Laksono

发明人： Jason CK Chan ,  Milivoje Aleksic ,  Antonio Asaro ,  James Doyle ,  Indra Laksono

IPC分类号： G06F1500

CPC分类号： G06T15/005

摘要： To minimize CPU processing requirements for preparing and transferring data to a graphics processor, a graphics command processor is provided that supports application-level commands and references to the data associated with these commands. The graphics command processor parses the application command and data reference parameters, and subsequently fetches the appropriate graphics data from memory directly, without requiring additional CPU resources. To optimize performance, the graphics command processor fetches the data in parallel with the parsing and processing of the application commands from the CPU. The graphics command processor also includes a processing unit that converts the data from the format used by the application program to the format used for rendering. The graphics command processor creates the commands and data sequences used by a graphics engine to render each object of the image. Because the graphics command processor is closely coupled with the graphics engine, a number of efficiency can be gained, particularly with regard to the transfer of related data items. The processing of the primitive graphic command and data sequences by the graphics engine is asynchronous with the receipt of subsequent commands from the CPU and the fetching of subsequent data associated with the commands from the memory. In this manner, the latency associated with the conventional sequential processing of graphics data is minimized.

摘要翻译： 为了最大限度地减少CPU处理对图形处理器的准备和传输数据的需求，提供了一个图形命令处理器，支持应用级命令和对与这些命令相关联的数据的引用。 图形命令处理器解析应用程序命令和数据参考参数，然后直接从存储器中获取适当的图形数据，而不需要额外的CPU资源。 为了优化性能，图形命令处理器从CPU解析和处理应用程序命令并行获取数据。 图形命令处理器还包括处理单元，其将来自应用程序使用的格式的数据转换为用于呈现的格式。 图形命令处理器创建由图形引擎使用以渲染图像的每个对象的命令和数据序列。 因为图形命令处理器与图形引擎紧密耦合，所以可以获得许多效率，特别是关于相关数据项的传送。 图形引擎对原始图形命令和数据序列的处理与从CPU接收后续命令以及从与存储器的命令相关联的后续数据的获取是异步的。 以这种方式，与图形数据的常规顺序处理相关联的延迟最小化。

公开(公告)号：US6141024A

公开(公告)日：2000-10-31

申请号：US792784

申请日：1997-02-03

申请人： Indra Laksono ,  Antonio Asaro ,  Carl K. Mizuyabu

发明人： Indra Laksono ,  Antonio Asaro ,  Carl K. Mizuyabu

IPC分类号： G09G5/393 ,  G09G5/36

CPC分类号： G09G5/393

摘要： A rasterizer is used with a processor capable of providing raster data indicative of a pattern of pixels to be formed on a display. Each pixel has an attribute represented by a data value. The rasterizer has a replicator connected to form at least two copies of the raster data. A graphics engine is connected to use the at least two copies to store the data values in a memory. An output circuit is connected to use the data values stored in the memory to form the pattern on the display.

摘要翻译： 光栅化器与能够提供指示要在显示器上形成的像素的图案的光栅数据的处理器一起使用。 每个像素具有由数据值表示的属性。 光栅化器具有连接的复制器以形成光栅数据的至少两个副本。 连接图形引擎以使用至少两个副本将数据值存储在存储器中。 连接输出电路以使用存储在存储器中的数据值在显示器上形成图案。

公开(公告)号：US06546449B1

公开(公告)日：2003-04-08

申请号：US09347201

申请日：1999-07-02

申请人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

发明人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

IPC分类号： G06F1336

CPC分类号： G06F13/1684

摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

公开(公告)号：US07543101B2

公开(公告)日：2009-06-02

申请号：US10075149

申请日：2002-02-14

申请人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

发明人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

IPC分类号： G06F13/36

CPC分类号： G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

公开(公告)号：US06643756B1

公开(公告)日：2003-11-04

申请号：US09438308

申请日：1999-11-11

申请人： Milivoje Aleksic ,  Nader Akhlaghi-Tavasoli ,  Jason Chan ,  Carl Mizuyabu ,  Antonio Asaro

发明人： Milivoje Aleksic ,  Nader Akhlaghi-Tavasoli ,  Jason Chan ,  Carl Mizuyabu ,  Antonio Asaro

IPC分类号： G06F1200

CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F12/1081

摘要： A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

摘要翻译： 对存储器控制器进行视频或图形数据的请求。 当存储器控制器确定首先需要进行数据的转换时，向翻译器发出请求。 翻译器翻译来自存储器控制器的地址或请求翻译信息。 存储器控制器根据翻译器请求访问存储器。 如果请求用于翻译数据，则结果将被标记为翻译器。 如果翻译请求是用于翻译的地址，结果将被标记为原始请求。