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    Efficient Error Correction of Multi-Bit Errors
    1.
    发明申请
    Efficient Error Correction of Multi-Bit Errors 有权
    多位错误的高效纠错

    公开(公告)号：US20150039976A1

    公开(公告)日：2015-02-05

    申请号：US13958047

    申请日：2013-08-02

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Christian Badack

    IPC: H03M13/15 ,  G06F11/08

    CPC classification number: H03M13/15 ,  G06F11/08 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/6575

    Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·α3ji+Zw2·α2ji+Zw1·αji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)≠(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value Δvi= for the bit position i may then be determined on the basis of the error correction expression evaluated for αji.

    Abstract translation: 用于纠错的电路包括多个子电路，用于确定要用作纠错表达式（z1i，z2i，...，zmi）= Zw3·α3ji+ Zw2·α2ji中的系数的中间值Zw0，Zw1，Zw2，Zw3 + Zw1·αji+ Zw0。 中间值Zw0，Zw1，Zw2，Zw3根据子信号s1，s3，s5确定，以便在1位，2位或3位错误的情况下zi =（z1i，z2i，...， zi =（z1i，z2i，...，zmi）≠（0,0，...，0）当位位置i发生错误时， 当位位置i没有发生错误时。 然后可以基于针对αji评估的误差校正表达式来确定位位置i的校正值＆Dgr; vi =。

    Processing of data
    4.
    发明授权
    Processing of data 有权

    公开(公告)号：US11556412B2

    公开(公告)日：2023-01-17

    申请号：US16663839

    申请日：2019-10-25

    Applicant: Infineon Technologies AG

    Inventor： Christian Badack ,  Jessica Trebst ,  Michael Goessel ,  Klaus Oberlaender

    IPC: G06F11/10 ,  G06F9/38 ,  H03M13/00 ,  H03M13/15 ,  H03M13/13

    Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

    Determination and use of byte error position signals
    5.
    发明授权
    Determination and use of byte error position signals 有权

    公开(公告)号：US10812109B2

    公开(公告)日：2020-10-20

    申请号：US16178901

    申请日：2018-11-02

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

    IPC: H03M13/15

    Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

    DETERMINATION AND USE OF BYTE ERROR POSITION SIGNALS
    6.
    发明申请
    DETERMINATION AND USE OF BYTE ERROR POSITION SIGNALS 审中-公开

    公开(公告)号：US20190132006A1

    公开(公告)日：2019-05-02

    申请号：US16178901

    申请日：2018-11-02

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

    IPC: H03M13/15

    Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

    Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error
    7.
    发明申请
    Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error 有权
    用于校正包含相邻2位错误的3位错误的电路和方法

    公开(公告)号：US20140173386A1

    公开(公告)日：2014-06-19

    申请号：US13720780

    申请日：2012-12-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Thomas Kern ,  Ulrich Backhausen ,  Thomas Rabenalt ,  Christian Badack ,  Michael Goessel

    IPC: H03M13/15

    CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/616

    Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.

    Abstract translation: 提出了用于校正可能错误的二进制字v'= v'1中的错误的电路。 。 。 ，v'n相对于码字v = v1，。 。 。 ，vn，特别是包含相邻2位错误（突发错误）的3位错误。 电路包括校正子发生器和解码器。 使用修改的BCH，其中第一BCH码子矩阵的n个列向量作为列向量对配对，使得每个列向量对的两个列向量的分量XOR组合产生与所有列不同的相同列向量K 第一个BCH子矩阵的向量。 第二BCH子矩阵包括根据第一BCH子矩阵中的列向量的伽罗瓦域算术的作为第三功率的相应的列向量。 可以针对第一和第二子矩阵的列检查由发生器产生的综合征。

    Continuous error coding
    8.
    发明授权
    Continuous error coding 有权

    公开(公告)号：US11182246B1

    公开(公告)日：2021-11-23

    申请号：US16940751

    申请日：2020-07-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel ,  Klaus Oberlaender

    IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07

    Abstract: Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.

    DETECTING ADDRESS ERRORS
    9.
    发明申请
    DETECTING ADDRESS ERRORS 审中-公开

    公开(公告)号：US20200371864A1

    公开(公告)日：2020-11-26

    申请号：US16881473

    申请日：2020-05-22

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Klaus Oberlaender ,  Christian Badack ,  Michael Goessel

    IPC: G06F11/10 ,  G06F11/30 ,  G06F11/34 ,  H03M13/11

    Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

    ERROR CORRECTION
    10.
    发明申请
    ERROR CORRECTION 审中-公开

    公开(公告)号：US20170126253A1

    公开(公告)日：2017-05-04

    申请号：US15337286

    申请日：2016-10-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

    IPC: H03M13/29 ,  H03M13/15 ,  G06F11/10

    CPC classification number: H03M13/2906 ,  G06F11/10 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/1575

    Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.

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