-
公开(公告)号：US12147303B2
公开(公告)日：2024-11-19
申请号：US18159365
申请日：2023-01-25
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Alexander Klockmann , Thomas Rabenalt
IPC: G06F11/10
Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.
-
公开(公告)号：US20220345157A1
公开(公告)日：2022-10-27
申请号：US17719648
申请日：2022-04-13
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Alexander Klockmann , Thomas Rabenalt
IPC: H03M13/15
Abstract: A solution for detecting a multibyte error in a code word of a shortened error code is proposed, the shortened error code is a τ-byte-correcting error code, wherein bytes of the code word of the shortened error code determined a first range, the non-correctable multibyte error is detected if at least one of the following conditions is met: (a) at least one error position signal does not lie in the first range; (b) at least one error position signal indicates at least one error but fewer than terrors in the first range and no 1-byte error to (τ−1)-byte error is present.
-
公开(公告)号：US20220231704A1
公开(公告)日：2022-07-21
申请号：US17579721
申请日：2022-01-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Thomas Rabenalt
IPC: H03M13/15
Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.
-
公开(公告)号：US20190312601A1
公开(公告)日：2019-10-10
申请号：US16380089
申请日：2019-04-10
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Thomas Rabenalt
Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.
-
公开(公告)号：US10133626B2
公开(公告)日：2018-11-20
申请号：US15232323
申请日：2016-08-09
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.
-
Patent Agency Ranking
公开(公告)号：US20150039976A1
公开(公告)日：2015-02-05
申请号：US13958047
申请日：2013-08-02
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Christian Badack
CPC classification number: H03M13/15 , G06F11/08 , H03M13/152 , H03M13/1575 , H03M13/6575
Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·α3ji+Zw2·α2ji+Zw1·αji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)≠(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value Δvi= for the bit position i may then be determined on the basis of the error correction expression evaluated for αji.
Abstract translation: 用于纠错的电路包括多个子电路，用于确定要用作纠错表达式（z1i，z2i，...，zmi）= Zw3·α3ji+ Zw2·α2ji中的系数的中间值Zw0，Zw1，Zw2，Zw3 + Zw1·αji+ Zw0。 中间值Zw0，Zw1，Zw2，Zw3根据子信号s1，s3，s5确定，以便在1位，2位或3位错误的情况下zi =（z1i，z2i，...， zi =（z1i，z2i，...，zmi）≠（0,0，...，0）当位位置i发生错误时， 当位位置i没有发生错误时。 然后可以基于针对αji评估的误差校正表达式来确定位位置i的校正值＆Dgr; vi =。
-
公开(公告)号：US20130339819A1
公开(公告)日：2013-12-19
申请号：US13914073
申请日：2013-06-10
Applicant: Infineon Technologies AG
Inventor： Georg Georgakos , Michael Goessel , Egor Sogomonyan
IPC: G06F11/08
CPC classification number: G06F11/08 , G06F11/1008 , H03K19/0033 , H03K19/23
Abstract: Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.
Abstract translation: 提供了与容错存储器相关的方法和装置。 在一个示例实施例中，来自至少三个存储器装置的输出信号被提供给纠错装置。 错误校正装置输出校正数据值，使得当读取的数据值匹配时，输出该数据值，并且在数据值不匹配的至少一个状态中保留先前输出的数据值 。
-
公开(公告)号：US20240146333A1
公开(公告)日：2024-05-02
申请号：US18487267
申请日：2023-10-16
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
CPC classification number: H03M13/1515 , H03M13/1575 , H03M13/6516
Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation τ into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.
-
公开(公告)号：US20240126640A1
公开(公告)日：2024-04-18
申请号：US18390065
申请日：2023-12-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Thomas Rabenalt , Michael Goessel
CPC classification number: G06F11/08 , G06F11/1012 , G11C29/18 , G11C29/42 , G11C29/4401
Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.
-
公开(公告)号：US20240048159A1
公开(公告)日：2024-02-08
申请号：US18355692
申请日：2023-07-20
Applicant: Infineon Technologies AG
Inventor： Jens Rosenbusch , Klaus Oberländer , Georg Duchrau , Michael Goessel
CPC classification number: H03M13/1174 , H03M13/616
Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.
-
-
-
-
-
-
-
-
-
Search Results
71
records
(took 0.023 seconds)
