公开(公告)号：US11373857B2

公开(公告)日：2022-06-28

申请号：US16411784

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Iris Moder ,  Petra Fischer

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/304 ,  H01L21/3065

Abstract: One or more semiconductor manufacturing methods and/or semiconductor arrangements are provided. In an embodiment, a silicon carbide (SiC) layer is provided. The SiC layer has a first portion overlying a second portion. The first portion has a first side distal the second portion and a second side proximal the second portion. The first portion is converted into a porous layer overlying the second portion. The porous layer has a first side distal the second portion and a second side proximal the second portion. The porous layer is removed to expose a first side of the second portion. After removing the porous layer, the first side of the second portion has a surface roughness less than a surface roughness of the first side of the first portion and/or less than a surface roughness of the first side of the porous layer.

公开(公告)号：US09773736B2

公开(公告)日：2017-09-26

申请号：US14607708

申请日：2015-01-28

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

公开(公告)号：US20150044856A1

公开(公告)日：2015-02-12

申请号：US14525233

申请日：2014-10-28

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Petra Fischer

IPC: H01L21/78 ,  H01L21/322

CPC classification number: H01L21/78 ,  H01L21/3043 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/322 ,  H01L21/6835 ,  H01L21/6836 ,  H01L29/1608 ,  H01L2221/68327

Abstract: A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.

Abstract translation: 一种用于分离半导体管芯的方法包括在半导体晶片上形成多孔区域，并使用机械或其他方式在多孔区域分离管芯。

公开(公告)号：US20160126197A1

公开(公告)日：2016-05-05

申请号：US14932548

申请日：2015-11-04

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Dirk Ahlers ,  Ulrike Fastner ,  Petra Fischer ,  Karl-Heinz Gasser ,  Stephan Henneck ,  Stefan Krivec ,  Florian Weilnboeck

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/45 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/83 ,  H01L29/45 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.

Abstract translation: 半导体器件包括具有第一主表面和第二主表面的半导体芯片。 芯片电极设置在第一主表面上。 芯片电极包括第一金属层，并且其中第一金属层布置在半导体芯片和第二金属层之间。

公开(公告)号：US20180358299A1

公开(公告)日：2018-12-13

申请号：US16003687

申请日：2018-06-08

Applicant: Infineon Technologies AG

Inventor： Petra Fischer ,  Johanna Schlaminger ,  Monika Cornelia Voerckel ,  Peter Zorn

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76852 ,  H01L23/5286

Abstract: According to various embodiments, a method for processing an electronic device may include: forming a patterned hard mask layer over a power metallization layer, the patterned hard mask layer exposing at least one surface region of the power metallization layer; and patterning the power metallization layer by wet etching of the exposed at least one surface region of the power metallization layer.

公开(公告)号：US20150064877A1

公开(公告)日：2015-03-05

申请号：US14014699

申请日：2013-08-30

Applicant: Infineon Technologies AG

Inventor： Petra Fischer ,  Michael Roesner ,  Gudrun Stranzl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/03001

Abstract: A method for processing a semiconductor wafer in accordance with various embodiments may include: providing a semiconductor wafer including at least one chip and at least one kerf region adjacent to the at least one chip, the kerf region including at least one auxiliary structure; applying a mask layer to the semiconductor wafer; removing the at least one auxiliary structure in the at least one kerf region; removing the applied mask layer; and separating the semiconductor wafer along the at least one kerf region.

Abstract translation: 根据各种实施例的用于处理半导体晶片的方法可以包括：提供包括至少一个芯片的半导体晶片和与所述至少一个芯片相邻的至少一个切割区域，所述切割区域包括至少一个辅助结构; 对半导体晶片施加掩模层; 去除所述至少一个切口区域中的所述至少一个辅助结构; 去除所施加的掩模层; 以及沿着所述至少一个切口区域分离所述半导体晶片。

公开(公告)号：US10461031B2

公开(公告)日：2019-10-29

申请号：US16003687

申请日：2018-06-08

Applicant: Infineon Technologies AG

Inventor： Petra Fischer ,  Johanna Schlaminger ,  Monika Cornelia Voerckel ,  Peter Zorn

IPC: H01L21/283 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

Abstract: According to various embodiments, a method for processing an electronic device may include: forming a patterned hard mask layer over a power metallization layer, the patterned hard mask layer exposing at least one surface region of the power metallization layer; and patterning the power metallization layer by wet etching of the exposed at least one surface region of the power metallization layer.

公开(公告)号：US20160218033A1

公开(公告)日：2016-07-28

申请号：US14607708

申请日：2015-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract translation: 在半导体衬底上形成金属化层的方法包括在层间电介质层上沉积扩散阻挡衬垫的覆盖层，以及在扩散阻挡衬里上沉积中间层的覆盖层。 包含铜的功率金属层的覆盖层沉积在中间层上。 中间层包括多数元素和铜的固溶体。 中间层具有与功率金属层不同的蚀刻选择性。 在沉积功率金属层之后，构建功率金属层，中间层和扩散阻挡衬里。

公开(公告)号：US09059273B2

公开(公告)日：2015-06-16

申请号：US14014699

申请日：2013-08-30

Applicant: Infineon Technologies AG

Inventor： Petra Fischer ,  Michael Roesner ,  Gudrun Stranzl

IPC: H01L21/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/03001

Abstract: A method for processing a semiconductor wafer in accordance with various embodiments may include: providing a semiconductor wafer including at least one chip and at least one kerf region adjacent to the at least one chip, the kerf region including at least one auxiliary structure; applying a mask layer to the semiconductor wafer; removing the at least one auxiliary structure in the at least one kerf region; removing the applied mask layer; and separating the semiconductor wafer along the at least one kerf region.

Abstract translation: 根据各种实施例的用于处理半导体晶片的方法可以包括：提供包括至少一个芯片的半导体晶片和与所述至少一个芯片相邻的至少一个切割区域，所述切割区域包括至少一个辅助结构; 对半导体晶片施加掩模层; 去除所述至少一个切口区域中的所述至少一个辅助结构; 去除所施加的掩模层; 以及沿着所述至少一个切口区域分离所述半导体晶片。