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公开(公告)号：US20210043605A1
公开(公告)日：2021-02-11
申请号：US16939130
申请日：2020-07-27
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller , Andressa Colvero Schittler , Daniel Domes , Andre Lenze
IPC: H01L25/065 , H01L23/538 , H01L23/00 , H01L23/367 , H01L23/64 , H01L23/049
Abstract: A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.
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公开(公告)号：US20180316277A1
公开(公告)日：2018-11-01
申请号：US15965491
申请日：2018-04-27
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller
Abstract: First and second semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series between first and second supply nodes, are connected with each other via a first common node. Third and fourth semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series and between a third supply node and the second supply node, are connected with each other via a second common node. A fifth semiconductor main-element has a control electrode and a load path operatively connected between the first common node and an output node. A sixth semiconductor main-element has a control electrode and a load path operatively connected between the second common node and the output node. At least two of the controllable semiconductor main-elements each include a plurality of identical controllable semiconductor subcomponents.
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公开(公告)号：US11942452B2
公开(公告)日：2024-03-26
申请号：US16939130
申请日：2020-07-27
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller , Andressa Colvero Schittler , Daniel Domes , Andre Lenze
IPC: H01L25/065 , H01L23/00 , H01L23/049 , H01L23/367 , H01L23/538 , H01L23/64
CPC classification number: H01L25/0655 , H01L23/049 , H01L23/367 , H01L23/5383 , H01L23/642 , H01L24/48 , H01L2224/48225
Abstract: A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.
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Patent Agency Ranking
公开(公告)号：US11133303B2
公开(公告)日：2021-09-28
申请号：US16893058
申请日：2020-06-04
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller , Stefan Buschhorn , Johannes Georg Laven
IPC: H01L29/74 , H01L27/06 , H01L29/423
Abstract: An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.
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公开(公告)号：US20210119003A1
公开(公告)日：2021-04-22
申请号：US17066954
申请日：2020-10-09
Applicant: Infineon Technologies AG
Inventor： Vera Van Treek , Roman Baburske , Christian Jaeger , Christian Robert Mueller , Franz-Josef Niedernostheide , Frank Dieter Pfirsch , Alexander Philippou , Judith Specht
IPC: H01L29/417 , H01L29/06 , H01L23/535 , H01L23/00 , H01L29/739
Abstract: A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.
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公开(公告)号：US11362080B2
公开(公告)日：2022-06-14
申请号：US16697444
申请日：2019-11-27
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller , Christoph Urban
IPC: H01L25/18 , H01L23/538 , H01L23/00 , H01L23/367 , H02M7/5387
Abstract: A semiconductor arrangement includes at least one switching device, electrically coupled between a first terminal and a second terminal, at least one diode, coupled in parallel to the at least one switching device between the first terminal and the second terminal, at least one bonding pad, and at least one electrically connecting element. Each of the at least one electrically connecting element is arranged to electrically couple one of the at least one switching device to one of the at least one diode. Each electrically connecting element includes a first end, a second end, and a middle section, and for at least one of the electrically connecting element, the first end is mechanically coupled to the respective switching device, the second end is mechanically coupled to the respective diode, and the middle section is mechanically coupled to at least one of the at least one bonding pad.
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公开(公告)号：US11257914B2
公开(公告)日：2022-02-22
申请号：US17066954
申请日：2020-10-09
Applicant: Infineon Technologies AG
Inventor： Vera Van Treek , Roman Baburske , Christian Jaeger , Christian Robert Mueller , Franz-Josef Niedernostheide , Frank Dieter Pfirsch , Alexander Philippou , Judith Specht
IPC: H01L29/417 , H01L29/06 , H01L23/535 , H01L23/00 , H01L29/739
Abstract: A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.
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公开(公告)号：US10186986B2
公开(公告)日：2019-01-22
申请号：US15965491
申请日：2018-04-27
Applicant: Infineon Technologies AG
Inventor： Christian Robert Mueller
Abstract: First and second semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series between first and second supply nodes, are connected with each other via a first common node. Third and fourth semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series and between a third supply node and the second supply node, are connected with each other via a second common node. A fifth semiconductor main-element has a control electrode and a load path operatively connected between the first common node and an output node. A sixth semiconductor main-element has a control electrode and a load path operatively connected between the second common node and the output node. At least two of the controllable semiconductor main-elements each include a plurality of identical controllable semiconductor subcomponents.
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