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公开(公告)号：US11831306B2
公开(公告)日：2023-11-28
申请号：US17836181
申请日：2022-06-09
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , David Zipperstein , Juergen Schaefer , Holger Dienst , Markus Bichl , Ralph Mueller-Eschenbach , Arndt Voigtlaender
Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.
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公开(公告)号：US20220399886A1
公开(公告)日：2022-12-15
申请号：US17836181
申请日：2022-06-09
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , David Zipperstein , Juergen Schaefer , Holger Dienst , Markus Bichl , Ralph Mueller-Eschenbach , Arndt Voigtlaender
Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.
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公开(公告)号：US11942959B2
公开(公告)日：2024-03-26
申请号：US17487199
申请日：2021-09-28
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Stefan Koeck , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , David Zipperstein
CPC classification number: H03M1/1014 , H03M1/0626 , H03M3/464
Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.
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公开(公告)号：US11621717B1
公开(公告)日：2023-04-04
申请号：US17519759
申请日：2021-11-05
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , David Zipperstein
Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.
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