公开(公告)号：US20190319582A1

公开(公告)日：2019-10-17

申请号：US16378046

申请日：2019-04-08

Applicant: Infineon Technologies AG

Inventor： Lukas HESCHL ,  Rainer Stuhlberger

IPC: H03B5/12 ,  H03L7/08 ,  H03L7/099 ,  H03L7/189 ,  H03L7/089

Abstract: A method for a radar device is described. According to one example implementation, the method comprises generating an RF signal using a voltage-controlled oscillator (VCO), wherein the frequency of the RF signal depends on a first tuning voltage and a second tuning voltage. The method also comprises setting the second tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency. The first tuning voltage is changed in such a manner that the second tuning voltage set by the phase-locked loop corresponds approximately to a predefined value. Another example implementation relates to a method for a radar device comprising: generating an RF signal using a VCO, wherein the frequency of the RF signal depends on a tuning voltage, setting the tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency, and determining a differential VCO gain of the VCO. The bandwidth of the phase-locked loop is set on the basis of the determined VCO gain.

公开(公告)号：US20200072942A1

公开(公告)日：2020-03-05

申请号：US16554066

申请日：2019-08-28

Applicant: Infineon Technologies AG

Inventor： Bernhard GRESLEHNER-NIMMERVOLL ,  Bernhard GSTOETTENBAUER ,  Lukas HESCHL ,  Evangelos KOUTSOURADIS ,  Alexander ONIC

IPC: G01S7/40 ,  G01S13/28 ,  G01S7/28

Abstract: One example of a radar device includes a phase-locked loop for generating a radiofrequency signal. The phase-locked loop has a multi-modulus divider. The radar device furthermore comprises a delta-sigma modulator for generating a modulated signal for the multi-modulus divider, and a signal generator for generating an input signal for the delta-sigma modulator. The radar device has monitoring circuits, wherein a first monitoring circuit is configured to monitor a locked state of the phase-locked loop, a second monitoring circuit is configured to monitor the delta-sigma modulator, and a third monitoring circuit is configured to monitor the signal generator.

公开(公告)号：US20180175868A1

公开(公告)日：2018-06-21

申请号：US15843589

申请日：2017-12-15

Applicant: Infineon Technologies AG

Inventor： Rainer STUHLBERGER ,  Lukas HESCHL

IPC: H03L7/14 ,  H03L7/081 ,  H03L7/10 ,  H03G3/30

CPC classification number: H03L7/146 ,  G01S7/35 ,  G01S13/343 ,  G01S2013/9321 ,  H03G3/3047 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/101

Abstract: A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.