公开(公告)号：US20180366397A1

公开(公告)日：2018-12-20

申请号：US16114900

申请日：2018-08-28

申请人： ROHM CO., LTD.

发明人： Shoji YASUNAGA ,  Akihiro KOGA

IPC分类号： H01L23/495 ,  H01L23/373 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/52 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48997 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49505 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83385 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85439 ,  H01L2224/85951 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/20753 ,  H01L2924/2076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.

公开(公告)号：US20180197846A1

公开(公告)日：2018-07-12

申请号：US15911398

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L21/66 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L22/14 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/64 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/2076 ,  H01L2924/014

摘要： A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.

公开(公告)号：US20180090463A1

公开(公告)日：2018-03-29

申请号：US15816568

申请日：2017-11-17

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yukihiro SATOU ,  Toshiyuki HATA

IPC分类号： H01L23/00 ,  H01L29/78 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L29/7827 ,  H01L2224/02166 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/2075 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206

摘要： A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

公开(公告)号：US09908203B2

公开(公告)日：2018-03-06

申请号：US15420140

申请日：2017-01-31

申请人： MEDIATEK Inc.

发明人： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC分类号： H01L25/10 ,  B23K35/02 ,  H01L23/498 ,  B23K35/26 ,  B23K101/40

CPC分类号： B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

摘要： A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

公开(公告)号：US20180047714A1

公开(公告)日：2018-02-15

申请号：US15559834

申请日：2016-03-23

申请人： GD MIDEA AIRCONDITIONING EQUIPMENT CO., LTD. ,  MIDEA GROUP CO., LTD.

发明人： Yuxiang Feng

IPC分类号： H01L25/18 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/06 ,  H05K1/18 ,  H05K1/02 ,  H01L23/053 ,  H05K3/34 ,  H05K3/28 ,  H01L25/00 ,  H01L23/373

CPC分类号： H01L25/18 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/565 ,  H01L22/14 ,  H01L23/053 ,  H01L23/06 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83815 ,  H01L2224/85815 ,  H01L2224/92247 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M7/003 ,  H02M7/5387 ,  H05K1/0204 ,  H05K1/111 ,  H05K1/181 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3494 ,  H05K7/209 ,  H05K2201/066 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10287 ,  H05K2201/10318 ,  H05K2201/10522 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/162 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/2076

摘要： An intelligent power module and a manufacturing method thereof are provided. The intelligent power module includes a radiator, an insulating layer, a circuit wiring, a circuit component and a metal wire. At least part of a lower surface of the radiator is defined as a heat dissipating area, the heat dissipating area is provided with a heat dissipating corrugation, the insulating layer is provided to an upper surface of the radiator, the circuit wiring is provided to the insulating layer, and the circuit component is provided to the circuit wiring and is connected to the circuit wiring via the metal wire.

公开(公告)号：US20180012860A1

公开(公告)日：2018-01-11

申请号：US15712680

申请日：2017-09-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/525

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

摘要： In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

公开(公告)号：US09859242B2

公开(公告)日：2018-01-02

申请号：US15419924

申请日：2017-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Yi-Wen Wu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

公开(公告)号：US09741805B2

公开(公告)日：2017-08-22

申请号：US14929912

申请日：2015-11-02

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takeyoshi Nishimura

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/10 ,  H01L23/00

CPC分类号： H01L29/41741 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/7392 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48455 ,  H01L2224/4847 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/2076 ,  H01L2924/01028 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01012 ,  H01L2924/0103 ,  H01L2924/013 ,  H01L2924/01008

摘要： A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.

公开(公告)号：US20170236813A1

公开(公告)日：2017-08-17

申请号：US15585971

申请日：2017-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L22/14 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/64 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/2076 ,  H01L2924/014

摘要： Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package.

公开(公告)号：US09728527B2

公开(公告)日：2017-08-08

申请号：US14925807

申请日：2015-10-28

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC分类号： H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L21/311 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/32 ,  H01L24/33 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/08146 ,  H01L2224/0823 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/13616 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4805 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/4903 ,  H01L2224/49426 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/45616 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/45099

摘要： An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.