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    System and method of monitoring a switching transistor
    2.
    发明授权
    System and method of monitoring a switching transistor 有权

    公开(公告)号：US10895601B2

    公开(公告)日：2021-01-19

    申请号：US16409131

    申请日：2019-05-10

    Applicant: Infineon Technologies AG

    Inventor： Matthias Bogus ,  Jens Barrenscheen ,  Christian Heiling ,  Benno Koeppl ,  Markus Zannoth

    IPC: H02P27/08 ,  H02H7/08 ,  G01R31/327 ,  H03K17/082 ,  G01R31/26

    Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

    Open pin detection for analog-to-digital converter
    3.
    发明授权
    Open pin detection for analog-to-digital converter 有权

    公开(公告)号：US10574258B1

    公开(公告)日：2020-02-25

    申请号：US16387050

    申请日：2019-04-17

    Applicant: Infineon Technologies AG

    Inventor： Siegfried Albel ,  Matthias Bogus ,  Christian Heiling ,  Jaafar Mejri ,  Markus Zannoth

    IPC: H03M3/00 ,  H03M7/30

    Abstract: A method includes applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin to a digital stream using a Sigma-Delta modulator; converting the digital stream to a first digital output signal proportional to the analog signal in a first input range between a first analog signal value and a second analog signal value, where the first input range corresponds to a pre-determined range of the analog signal smaller than a full-scale input range of the analog signal; converting the digital stream to a second output signal; comparing the second output signal to a first threshold corresponding to a third analog signal value at the input pin that is outside of the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

    Three level gate monitoring
    4.
    发明授权
    Three level gate monitoring 有权

    公开(公告)号：US10215795B1

    公开(公告)日：2019-02-26

    申请号：US15953146

    申请日：2018-04-13

    Applicant: Infineon Technologies AG

    Inventor： Markus Zannoth ,  Jaafar Mejri

    IPC: H03K5/153 ,  G01R31/26 ,  H02M1/08 ,  G01R19/165 ,  H03K17/0812 ,  H03K17/08

    Abstract: A method of monitoring a gate of a transistor includes monitoring a gate voltage of the transistor; measuring a first time difference between when a gate control signal is asserted and when the gate voltage of the transistor crosses a first voltage threshold based on the monitoring; measuring a second time difference between when the gate voltage of the transistor crosses the first voltage threshold and when the gate voltage of the transistor crosses a second voltage threshold based on the monitoring; and determining whether the first time difference falls within a first time window, and whether the second time difference falls within a second time window.

    CONFIGURATION OF GATE DRIVERS WITH SHOOT THROUGH PROTECTION
    5.
    发明公开
    CONFIGURATION OF GATE DRIVERS WITH SHOOT THROUGH PROTECTION 审中-公开

    公开(公告)号：US20240348149A1

    公开(公告)日：2024-10-17

    申请号：US18300242

    申请日：2023-04-13

    Applicant: Infineon Technologies AG

    Inventor： Alexander Mayer ,  Jens Barrenscheen ,  Christian Heiling ,  Markus Zannoth

    IPC: H02M1/088 ,  H02M1/32 ,  H02M1/38

    CPC classification number: H02M1/088 ,  H02M1/32 ,  H02M1/38

    Abstract: In general, the disclosure describes circuits and techniques to operate power switch driver circuits as well as techniques to dynamically change configuration parameters. The power switch driver circuit of this disclosure may be configured to received communication signals along the same signal paths as for pulse modulated switching control signals. In other words, the power switch driver circuit may receive a main function signaling, switching the power switches on and off, overlaid with a secondary function signaling, communication, which may include configuration parameters. In this manner the power switch driver circuit may receive both switching (commutation) function and communication function along the same signal path.

    INTEGRATED CIRCUIT ARRANGEMENT, METHOD AND SYSTEM FOR USE IN A SAFETY-CRITICAL APPLICATION
    7.
    发明申请
    INTEGRATED CIRCUIT ARRANGEMENT, METHOD AND SYSTEM FOR USE IN A SAFETY-CRITICAL APPLICATION 有权
    集成电路布置，安全关键应用中的使用方法和系统

    公开(公告)号：US20140285032A1

    公开(公告)日：2014-09-25

    申请号：US14219805

    申请日：2014-03-19

    Applicant: Infineon Technologies AG

    Inventor： Markus Zannoth

    IPC: H02H9/00

    CPC classification number: H02H9/00 ,  G01R19/16576 ,  G01R31/025 ,  Y10T307/858

    Abstract: An integrated circuit arrangement (100, 200, 600) has a first circuit part (102, 202, 602) which can be supplied with a first supply voltage (106, 206, 606), and a second circuit part (104, 204, 604) which can be supplied with a second supply voltage (108, 208, 608). The first circuit part and the second circuit part are arranged in a manner spatially separate from one another. The first circuit part has a first conduction element (110, 210, 310, 410, 610), and the second circuit part has a second conduction element (112, 212, 312, 412, 612). The integrated circuit arrangement also has a third conduction element (114, 214, 314, 414, 614), the third conduction element being arranged between the first conduction element and the second conduction element in such a manner that the third conduction element is arranged adjacent to the first conduction element and the third conduction element is also arranged adjacent to the second conduction element. The third conduction element can be supplied with a reference potential (116, 216, 616) at a first end, and the third conduction element is connected, at a second end, to an evaluation circuit (118, 218, 618) for detecting a short circuit from the first conduction element to the third conduction element or from the second conduction element to the third conduction element.

    Abstract translation: 集成电路装置（100,200,600）具有可被提供有第一电源电压（106,206,606）的第一电路部分（102,202,602）和第二电路部分（104,204,602） 604），其可以被提供有第二电源电压（108,208,608）。 第一电路部分和第二电路部分以空间上彼此分离的方式排列。 第一电路部分具有第一导电元件（110,210,310,410,610），并且第二电路部分具有第二导电元件（112,212,312,412,612）。 集成电路装置还具有第三导电元件（114,214,314,414,614），所述第三导电元件被布置在第一导电元件和第二导电元件之间，使得第三导电元件被布置为相邻 第一导电元件和第三导电元件也被布置成与第二导电元件相邻。 第三导电元件可以在第一端处被提供有参考电位（116,216,616），并且第三导电元件在第二端被连接到评估电路（118,218,618），用于检测 从第一导电元件到第三导电元件或从第二导电元件到第三导电元件的短路。

    Integrated circuit arrangement, method and system for use in a safety-critical application
    10.
    发明授权
    Integrated circuit arrangement, method and system for use in a safety-critical application 有权

    公开(公告)号：US09647449B2

    公开(公告)日：2017-05-09

    申请号：US14219805

    申请日：2014-03-19

    Applicant: Infineon Technologies AG

    Inventor： Markus Zannoth

    IPC: H02H9/00 ,  G01R31/02 ,  G01R19/165

    CPC classification number: H02H9/00 ,  G01R19/16576 ,  G01R31/025 ,  Y10T307/858

    Abstract: An integrated circuit arrangement (100, 200, 600) has a first circuit part (102, 202, 602) which can be supplied with a first supply voltage (106, 206, 606), and a second circuit part (104, 204, 604) which can be supplied with a second supply voltage (108, 208, 608). The first circuit part and the second circuit part are arranged in a manner spatially separate from one another. The first circuit part has a first conduction element (110, 210, 310, 410, 610), and the second circuit part has a second conduction element (112, 212, 312, 412, 612). The integrated circuit arrangement also has a third conduction element (114, 214, 314, 414, 614), the third conduction element being arranged between the first conduction element and the second conduction element in such a manner that the third conduction element is arranged adjacent to the first conduction element and the third conduction element is also arranged adjacent to the second conduction element. The third conduction element can be supplied with a reference potential (116, 216, 616) at a first end, and the third conduction element is connected, at a second end, to an evaluation circuit (118, 218, 618) for detecting a short circuit from the first conduction element to the third conduction element or from the second conduction element to the third conduction element.

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